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Technical Data
MSC8103/D Rev. 7 , 1/2004 Networking Digital Signal Processor
(mask set 2K87M)
CPM MCC / UART / HDLC / Transparent / Ethernet / Fast Ethernet / ATM / SCC 3 x FCC 2 x MCC 4 x SCC 2 x SMC SPI I2C UTOPIA Interface MII Interrupt Controller Timers Parallel I/O Baud Rate Generators Dual Ported RAM 2 x SDMA RISC
SIU 64-bit System Bus MEMC PIT System Protection Reset Control Clock Control SIC_EXT Interrupts Bridge SIC 64/32-bit System Bus
Serial Interface and TSA
DMA Engine
TDMs
The Motorola MSC8103 16-bit Digital Signal Processor (DSP) is the first member of the family of DSPs based on the SC140 DSP core. The MSC8103 is offered in two core speed levels: 275 and 300 MHz.
{ **
*
Other Peripherals Extended Core Program Sequencer SC140 Core JTAG Address Register File Address ALU EOnCETM Clock/PLL Data ALU Register File Data ALU Q2PPC Bridge
64-bit Local Bus
MEMC
128-bit QBus
PIC Interrupts 8/16-bit Host Interface
Boot ROM HDI16 SRAM 512 KB L1 Interface
Power Management
128-bit P-Bus 64-bit XA Data Bus 64-bit XB Data Bus
Figure 1. MSC8103 Block Diagram
What's New?
Rev. 7 includes the following changes: * Updated clock ranges in Table 2-11.
The Motorola MSC8103 DSP is a very versatile device that integrates the high-performance SC140 four-ALU (Arithmetic Logic Unit) DSP core along with 512 KB of internal memory, a Communications Processor Module (CPM), a 64-bit bus, a very flexible System Integration Unit (SIU), and a 16-channel DMA engine on a single device. With its four-ALU core, the MSC8103 can execute up to four multiply-accumulate (MAC) operations in a single clock cycle. The MSC8103 CPM is a 32-bit RISC-based communications protocol engine that can network to Time-Division Multiplexed (TDM) highways, Ethernet, and
Asynchronous Transfer mode (ATM) backbones. The MSC8103 60x-compatible bus interface facilitates its connection to multi-master system architectures. The very large internal memory, 512 KB, reduces the need for external program and data memories. The MSC8103 offers 1200 DSP MMACS performance using an internal 300 MHz clock with a 1.6 V core and independent 3.3 V input/output (I/O). Figure 1 shows a block diagram of the MSC8103 processor.
Table of Contents
MSC8103 Features............................................................................................................................................. iii Target Applications ............................................................................................................................................ iv Product Documentation...................................................................................................................................... iv
Chapter 1
Signal/ Connection Descriptions
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Signal Groupings.............................................................................................................................................. 1-1 Power Signals................................................................................................................................................... 1-4 Clock Signals ................................................................................................................................................... 1-5 Reset, Configuration, and EOnCE Event Signals ............................................................................................ 1-6 System Bus, HDI16, and Interrupt Signals ...................................................................................................... 1-8 Memory Controller Signals............................................................................................................................ 1-16 Communications Processor Module (CPM) Ports ......................................................................................... 1-18 JTAG Test Access Port Signals...................................................................................................................... 1-44 Reserved Signals ............................................................................................................................................ 1-45 Introduction ...................................................................................................................................................... 2-1 Absolute Maximum Ratings ............................................................................................................................ 2-1 Recommended Operating Conditions .............................................................................................................. 2-2 Thermal Characteristics ................................................................................................................................... 2-3 DC Electrical Characteristics ........................................................................................................................... 2-3 Clock Configuration......................................................................................................................................... 2-4 AC Timings ...................................................................................................................................................... 2-8 Pin-Out and Package Information .................................................................................................................... 3-1 Lidded FC-PBGA Package Description........................................................................................................... 3-1 Lidded FC-PBGA Package Mechanical Drawing.......................................................................................... 3-32 Thermal Design Considerations....................................................................................................................... 4-1 Electrical Design Considerations ..................................................................................................................... 4-2 Power Considerations....................................................................................................................................... 4-2 Layout Practices ............................................................................................................................................... 4-4
Chapter 2
Specifications
2.1 2.2 2.3 2.4 2.5 2.6 2.7
Chapter 3
Packaging
3.1 3.2 3.3
Chapter 4
Design Considerations
4.1 4.2 4.3 4.4
Index Ordering Information, Disclaimer, and Contact Information .................................................................. Back Cover
Data Sheet Conventions
OVERBAR "asserted" "deasserted"
Examples:
Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) Means that a high true (active high) signal is high or that a low true (active low) signal is low Means that a high true (active high) signal is low or that a low true (active low) signal is high
Signal/Symbol PIN PIN PIN PIN Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage VIL/VOL VIH/VOH VIH/VOH VIL/VOL
Note: Values for V IL, VOL, VIH , and VOH are defined by individual product specifications.
ii
MSC8103 Features
* SC140 Core -- Architecture optimized for efficient C/C++ code compilation -- Four 16-bit ALUs and two 32-bit AGUs -- 1200 DSP MMACS running at 300 MHz -- Very low power -- Variable-Length Execution Set (VLES) execution model -- JTAG/Enhanced OnCE debug port * Communications Processor Module (CPM) -- Programmable protocol machine using a 32-bit RISC engine -- 155 Mbps ATM interface (including AAL 0/1/2/5) -- 10/100 Mbit Ethernet interface -- Up to four E1/T1 interfaces or one E3/T3 interface and one E1/T1 interface -- HDLC support up to T3 rates, or 256 channels * 64- or 32-bit Wide Bus Interface -- Support for bursts for high efficiency -- Glueless interface to 60x-compatible bus systems -- Multi-master support * Programmable Memory Controller -- Control for up to eight banks of external memory -- User-programmable machines (UPM) allowing glueless interface to various memory types (SRAM, DRAM, EPROM, and Flash memory) and other user-definable peripherals -- Dedicated pipelined SDRAM memory interface * Large internal SRAM -- 256K 16-bit words (512 KB) -- Unified program and data space configurable by the application -- Word and byte addressable * DMA Controller -- 16 DMA channels, FIFO based, with burst capabilities -- Sophisticated addressing capabilities * Small Foot Print Package -- 17 mm x 17 mm lidded FC-PBGA package * Very Low Power Consumption * Separate power supply for internal logic (1.6 V) and for I/O (3.3 V) * Enhanced 16-bit Parallel Host Interface (HDI16) -- Supports a variety of microcontroller, microprocessor, and DSP bus interfaces * Phase-Lock Loops (PLLs) -- System PLL -- CPM DPLLs (SCC and SCM) * Process Technology -- Uses 0.13 micron copper interconnect process technology
iii
Target Applications
The MSC8103 targets applications requiring very high performance, very large amounts of internal memory, and such networking capabilities as: * * * * Third-generation wideband wireless infrastructure systems Packet Telephony systems Multi-channel modem banks Multi-channel xDSL
Product Documentation
The documents listed in Table 1 are required for a complete description of the MSC8103 and are necessary to design properly with the part. Documentation is available from the following sources (see back cover for detailed information): * * * * A local Motorola distributor A Motorola semiconductor sales office A Motorola Literature Distribution Center The World Wide Web (WWW) Table 1. MSC8103 Documentation
Name
MSC8103 Technical Data MSC8101 User's Guide MSC8103 Reference Manual SC140 DSP Core Reference Manual Application Notes
Description
MSC8103 features list and physical, electrical, timing, and package specifications Detailed functional description of the MSC8101 memory configuration, operation, and register programming. All details apply to the MSC8103. Detailed description of the MSC8103 processor core and instruction set Detailed description of the SC140 family processor core and instruction set Documents describing specific applications or optimized device operation including code examples
Order Number
MSC8103/D MSC8101UG/D
MSC8103RMA/D MNSC140CORE/D See the MSC8103 product website
iv
Chapter 1
Signal/ Connection Descriptions
1.1 Signal Groupings
The MSC8103 external signals are organized into functional groups, as shown in Table 1-1, Figure 1-1, and Figure 1-2. Table 1-1 lists the functional groups, the number of signal connections in each group, and references the table that gives a detailed listing of multiplexed signals within each group. Figure 1-1 shows MSC8103 external signals organized by function. Figure 1-2 indicates how the parallel input/output (I/O) ports signals are multiplexed. Because the parallel I/O design supported by the MSC8103 Communications Processor Module (CPM) is a subset of the parallel I/O signals supported by the MPC8260 device, port pins are not numbered sequentially. Table 1-1. MSC8103 Functional Signal Groupings
Number of Signal Connections
80 6 11 133 27 Port A Port B Port C Port D JTAG Test Access Port Reserved (denotes connections that are always reserved) 26 14 18 8 5 5
Functional Group
Detailed Description
Power (VCC, VDD, and GND) Clock Reset, Configuration, and EOnCE System Bus, HDI16, and Interrupts Memory Controller Communications Processor Module (CPM) Input/Output Parallel Ports
Table 1-2 on page 1-4 Table 1-3 on page 1-5 Table 1-4 on page 1-6 Table 1-5 on page 1-8 Table 1-6 on page 1-16 Table 1-7 on page 1-19 Table 1-8 on page 1-26 Table 1-9 on page 1-31 Table 1-10 on page 1-41 Table 1-11 on page 1-44 Table 1-12 on page 1-45
1-1
Signal Groupings
VDD VDDH VCCSYN VCCSYN1 GND GNDSYN GNDSYN1
14 25 1 1 37 1 1
P O W E R
Port A PA[31-6] For the signals multiplexed on Ports A-D, see Figure 1-2 Port B PB[31-18] Port C PC[31-22, 15-12, 7-4] Port D PD[31-29, 19-16, 7]
26
C P M I / O P O R T S
32 5 4 1 1 3 1 1 1 1 1 1 1 1 32 16 4 1

A[0-31] TT[0-4] TSIZ[0-3] TBST IRQ1 Reserved BR BG ABB TS AACK ARTRY DBG DBB D[0-31]
GBL BADDR[29-31]
IRQ[2-3, 5]
IRQ2
IRQ3 HDI16 Signals HD[0-15] HA[0-3] HCS1 Single DS Double DS HRW HRD/HRD HDS/HDS HWR/HWR Single HR Double HR HREQ/HREQ HTRQ/HTRQ HACK/HACK HRRQ/HRRQ HDSP HDDS H8BIT HCS2 Reserved DP0 DP1 DP2 DP3 DP4 DP5 DP6 DP7 Reserved IRQ1 Reserved Reserved DREQ3 DREQ4 DACK3 DACK4 EXT_Br2 EXT_BG2 EXT_DBG2 EXT_BR3 EXT_BG3 EXT_DBG3 IRQ6 IRQ7
14
D[32-47] D[48-51] D52 D53 D54 D55 D56 D57 D58 D59 D60 D[61-63]
18
6 0 x B U S
1 1 1 1 1 1 1 1 4 1
8
TMS TDI TCK TRST TDO

1 1 1 1 1
J T A G
Reserved IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 TA TEA NMI NMI_OUT PSDVAL IRQ7 CS[0-7] BCTL1 BADDR[27-28] ALE BCTL0 PWE[0-7] PSDA10 PSDWE POE PSDCAS PGTA PSDAMUX
EOnCE Event EED EE0 EE1 EE[2-3] EE[4-5]
RESET Configuration DBREQ HPE BTM[0-1] PORESET RSTCONF HRESET SRESET
1 1 1 2 2 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 8 1 2 1 1 8 1 1 1 1 1 1
INT_OUT
BNKSEL[0-2]
TC[0-2]
CLKIN MODCK[1-3] CLKOUT DLLIN

1 3 1 1
M E M C
PSDDQM[0-7]
PSDRAS PUPMWAIT PPBS
TEST THERM[1-2] SPARE1, SPARE5

1 2 2
PBS[0-7] PGPL0 PGPL1 PGPL2 PGPL3 PGPL4 PGPL5
Note:
Refer to the System Interface Unit (SIU) chapter in the MCS8103 Reference Manual for details on how to configure these pins.
Figure 1-1. MSC8103 External Signals
1-2
Signal Groupings
FCC1 ATM/UTOPIA MPHY MPHY Master Master mux poll dir. poll or Slave TXENB TXCLAV TXCLAV0 TXSOC (master) RXENB RXSOC (slave) RXCLAV RXCLAV0 TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0 FCC1 HDLC/ Ethernet transp. MII Serial COL CRS TX_ER TX_EN RX_DV RX_ER SDMA MSNUM0 MSNUM1
HDLC Nibble GPIO PA31 PA30 PA29 PA28 PA27 PA26 PA25 PA24 PA23 PA22 PA21 PA20 PA19 PA18 PA17 PA16 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PB31 PB30 PB29 PB28 PB27 PB26 PB25 PB24 PB23 PB22 PB21 PB20 PB19 BRGs Clocks Timers PB18 BRG1O CLK1 TGATE1 PC31 BRG2O CLK2 TOUT1 PC30 BRG3O CTS/CLSN SIU Timer Input BRG4O CLK5 TMCLK DMA DACK2 Ext. Req. EXT2 SCC1 LIST1 SMTXD CTS/CLSN CD/RENA LIST2 LIST4 LIST3 LIST1 LIST2 SMC1 SMTXD SMRXD RXD TXD RTS/TENA LIST3 LIST4 DRACK1/DONE1 DRACK2/DONE2 SPI BRG1O SPISEL SPICLK SPIMOSI BRG2O SPIMISO SMSYN DREQ2 DACK1 DREQ1 BRG5O BRG6O BRG7O BRG8O CLK3 TIN2 PC29
RTS
TXD3 TXD2 TXD1 TXD0 RXD0 RXD1 RXD2 RXD3
TXD RXD
TXD3 TXD2 TXD1 TXD0 RXD0 RXD1 RXD2 RXD3 SI1 TDMA1 Serial Nibble L1TXD L1TXD0 L1RXD L1RXD0 L1TSYNC L1RSYNC SI2 TDMB2 L1TXD L1RXD L1RSYNC L1TSYNC TDMC2 L1TXD L1RXD L1TSYNC L1RSYNC TDMD2 L1TXD L1RXD L1TSYNC L1RSYNC MSNUM2 MSNUM3 MSNUM4 MSNUM5
FCC2 HDLC/ HDLC Ethernet transp. MII Serial Nibble TX_ER RX_DV TX_EN RX_ER RTS COL CRS TXD3 TXD2 TXD1 TXD0 RXD0 RXD1 RXD2 RXD3 TXD RXD TXD3 TXD2 TXD1 TXD0 RXD0 RXD1 RXD2 RXD3 Ext. Req. EXT1 SCC1 CTS/CLSN
SMC2 SMTXD SMRXD SMSYN SCC2 RXD TXD RTS/TENA
L1TXD3 L1RXD3 L1RXD2 L1RXD1 L1TXD2 L1TXD1
I2C SDA SCL
TIN1/ CLK4 PC28 TOUT2 CLK5 TGATE2 PC27 CLK6 TOUT3 PC26 CLK7 CLK8 CLK9 CLK10 TIN4 TIN3/ TOUT4 PC25 PC24 PC23 PC22 PC15 PC14 PC13 PC12 PC7 PC6 PC5 PC4 PD31 PD30 PD29 PD19 PD18 PD17 PD16 PD7
TXADDR0 RXADDR0 TXADDR1 RXADDR1 TXADDR2/ TXADDR2 TXCLAV1 RXADDR2/ RXADDR2 RXCLAV1
CTS/CLSN CD/RENA FCC1 CTS CD FCC2 CTS CD
RXADDR3 RXCLAV2 TXADDR4 TXCLAV3 RXADDR4 RXCLAV3 RXPRTY TXPRTY TXADDR3 TXCLAV2
Figure 1-2. CPM Port A-D Pin Multiplexed Functionality 1-3
Power Signals
1.2 Power Signals
Table 1-2. Power and Ground Signal Inputs
Power Name
VDD
Description
Internal Logic Power VDD dedicated for use with the device core. The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VDD power rail. Input/Output Power This source supplies power for the I/O buffers. The user must provide adequate external decoupling capacitors. System PLL Power VCC dedicated for use with the system Phase Lock Loop (PLL). The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VCC power rail. SC140 PLL Power VCC dedicated for use with the SC140 core PLL. The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VCC power rail. System Ground An isolated ground for the internal processing logic. This connection must be tied externally to all chip ground connections, except GNDSYN and GNDSYN1. The user must provide adequate external decoupling capacitors. System PLL Ground Ground dedicated for system PLL use. The connection should be provided with an extremely low-impedance path to ground. SC140 PLL Ground 1 Ground dedicated for SC140 core PLL use. The connection should be provided with an extremely low-impedance path to ground.
VDDH
VCCSYN
VCCSYN1
GND
GNDSYN
GNDSYN1
1-4
Clock Signals
1.3 Clock Signals
Table 1-3. Clock Signals
Signal Name
CLKIN MODCK1
Type
Input Input
Signal Description
Clock In Primary clock input to the MSC8103 PLL. Clock Mode Input 1 Defines the operating mode of internal clock circuits. Transfer Code 0 Supplies information that can be useful for debugging bus transactions initiated by the MSC8103. Bank Select 0 Selects the SDRAM bank when the MSC8103 is in 60x-compatible bus mode. Clock Mode Input 2 Defines the operating mode of internal clock circuits. Transfer Code 1 Supplies information that can be useful for debugging bus transactions initiated by the MSC8103. Bank Select 1 Selects the SDRAM bank when the MSC8103 is in 60x-compatible bus mode. Clock Mode Input 3 Defines the operating mode of internal clock circuits. Transfer Code 2 Supplies information that can be useful for debugging bus transactions initiated by the MSC8103. Bank Select 2 Selects the SDRAM bank when the MSC8103 is in 60x-compatible bus mode. Clock Out The system bus clock. DLLIN Synchronizes with an external device. Note: When the DLL is disabled, connect this signal to GND.
TC0
Output
BNKSEL0 MODCK2
Output Input
TC1
Output
BNKSEL1 MODCK3
Output Input
TC2
Output
BNKSEL2 CLKOUT DLLIN
Output Output Input
1-5
Reset, Configuration, and EOnCE Event Signals
1.4 Reset, Configuration, and EOnCE Event Signals
Table 1-4. Reset, Configuration, and EOnCE Event Signals
Signal Name
DBREQ
Type
Input
Signal Description
Debug Request Determines whether to go into SC140 Debug mode when PORESET is deasserted. Enhanced OnCE (EOnCE) Event 0 After PORESET is deasserted, you can configure EE0 as an input (default) or an output.
EE01
Input
Debug request, enable Address Event Detection Channel 0, or generate one of the EOnCE events. Detection by Address Event Detection Channel 0. Used to trigger external debugging equipment. Host Port Enable When this pin is asserted during PORESET, the Host port is enabled, the system data bus is 32 bits wide, and the Host must program the reset configuration word. EOnCE Event 1 After PORESET is deasserted, you can configure EE1 as an input (default) or an output.
Output
HPE
Input
EE11
Input Output
Enable Address Event Detection Channel 1 or generate one of the EOnCE events. Debug Acknowledge or detection by Address Event Detection Channel 1. Used to trigger external debugging equipment. EOnCE Event 2 After PORESET is deasserted, you can configure EE2 as an input (default) or an output.
EE21
Input
Enable Address Event Detection Channel 2 or generate one of the EOnCE events or enable the Event Counter. Detection by Address Event Detection Channel 2. Used to trigger external debugging equipment. EOnCE Event 3 After PORESET is deasserted, you can configure EE3 as an input (default) or an output. See the Emulation and Debug chapter in the SC140 DSP Core Reference Manual for details on the ERCV Register.
Output
EE31
Input Output
Enable Address Event Detection Channel 3 or generate one of the EOnCE events. EOnCE Receive Register (ERCV) was read by the DSP. Used to trigger external debugging equipment.
1-6
Reset, Configuration, and EOnCE Event Signals
Table 1-4. Reset, Configuration, and EOnCE Event Signals (Continued)
Signal Name
BTM[0-1]
Type
Input
Signal Description
Boot Mode 0-1 Determines the MSC8103 boot mode when PORESET is deasserted. See the Emulation and Debug chapter in the SC140 DSP Core Reference Manual for details on how to set these pins. EOnCE Event 4 After PORESET is deasserted, you can configure EE4 as an input (default) or an output. See the Emulation and Debug chapter in the SC140 DSP Core Reference Manual for details on the ETRSMT Register.
EE41
Input Output
Enable Address Event Detection Channel 4 or generate one of the EOnCE events EOnCE Transmit Register (ETRSMT) was written by the DSP. Used to trigger external debugging equipment. EOnCE Event 5 After PORESET is deasserted, you can configure EE5 as an input (default) or an output.
EE51
Input Output
Enable Address Event Detection Channel 5. Detection by Address Event Detection Channel 5. Used to trigger external debugging equipment. Enhanced OnCE (EOnCE) Event Detection After PORESET is deasserted, you can configure EED as an input (default) or output:
EED1
Input Output
Enable the Data Event Detection Channel. Detection by the Data Event Detection Channel. Used to trigger external debugging equipment. Power-On Reset When asserted, this line causes the MSC8103 to enter power-on reset state. Reset Configuration Used during reset configuration sequence of the chip. A detailed explanation of its function is provided in the "Power-On Reset Flow" and "Hardware Reset Configuration" sections of the MSC8103 Reference Manual. Hard Reset When asserted, this open-drain line causes the MSC8103 to enter hard reset state. Soft Reset When asserted, this open-drain line causes the MSC8103 to enter soft reset state.
PORESET
Input
RSTCONF
Input
HRESET
Input
SRESET
Input
Note:
See the Emulation and Debug chapter in the SC140 DSP Core Reference Manual for details on how to configure these pins.
1-7
System Bus, HDI16, and Interrupt Signals
1.5 System Bus, HDI16, and Interrupt Signals
The system bus, HDI16, and interrupt signals are grouped together because they use a common set of signal lines. Individual assignment of a signal to a specific signal line is configured through registers in the System Interface Unit (SIU) and the Host Interface (HDI16). Table 1-5 describes the signals in this group. Note: To boot from the host interface, the HDI16 must be enabled by pulling up the HPE signal line during PORESET. If the HPE signal is pulled up, the configuration word must then be loaded from the host. The configuration word must set the Internal Space Port Size bit in the Bus Control Register (BCR[ISPS]) to change the system data bus width from 64 bits to 32 bits and reassign the upper 32 bits to their HDI16 functions. Never set the Host Port Enable (HEN) bit in the Host Port Control Register (HPCR) to enable the HDI16, unless the bus size is first changed from 64 bits to 32 bits by setting the BCR[ISPS] bit. Otherwise, unpredictable operation may occur.
Although there are eight interrupt request (IRQ) connections to the core processor, there are multiple external lines that can connect to these internal signal lines. After reset, the default configuration includes two IRQ1 and two IRQ7 input lines. The designer must select one line for each required interrupt and reconfigure the other external signal line or lines for alternate functions. Table 1-5.
Signal
A[0-31]
System Bus, HDI16, and Interrupt Signals
Description
Data Flow
Input/Output
Address Bus When the MSC8103 is in external master bus mode, these pins function as the address bus. The MSC8103 drives the address of its internal bus masters and responds to addresses generated by external bus masters. When the MSC8103 is in Internal Master Bus mode, these pins are used as address lines connected to memory devices and are controlled by the MSC8103 memory controller. Bus Transfer Type The bus master drives these pins during the address tenure to specify the type of transaction. Transfer Size The bus master drives these pins with a value indicating the number of bytes transferred in the current transaction. Bus Transfer Burst The bus master asserts this pin to indicate that the current transaction is a burst transaction (transfers four quad words). Interrupt Request 11 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Global1 When a master within the chip initiates a bus transaction, it drives this pin. When an external master initiates a bus transaction, it should drive this pin. Assertion of this pin indicates that the transfer is global and it should be snooped by caches in the system.
TT[0-4]
Input/Output
TSIZ[0-3]
Input/Output
TBST
Input/Output
IRQ1
Input
GBL
Input/Output
1-8
System Bus, HDI16, and Interrupt Signals
Table 1-5.
Signal
Reserved BADDR29
System Bus, HDI16, and Interrupt Signals (Continued)
Description
The primary configuration is reserved. Burst Address 291 One of five outputs of the memory controller. These pins connect directly to memory devices controlled by the MSC8103 memory controller. Interrupt Request 21 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. The primary configuration is reserved. Burst Address 301 One of five outputs of the memory controller. These pins connect directly to memory devices controlled by the MSC8103 memory controller. Interrupt Request 31 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. The primary configuration is reserved. Burst Address 311 One of five outputs of the memory controller. These pins connect directly to memory devices controlled by the MSC8103 memory controller. Interrupt Request 51 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Bus Request 2 An output when an external arbiter is used. The MSC8103 asserts this pin to request ownership of the bus. An input when an internal arbiter is used. An external master should assert this pin to request bus ownership from the internal arbiter. Bus Grant2 An output when an internal arbiter is used. The MSC8103 asserts this pin to grant bus ownership to an external bus master. An input when an external arbiter is used. The external arbiter should assert this pin to grant bus ownership to the MSC8103. Address Bus Busy1 The MSC8103 asserts this pin for the duration of the address bus tenure. Following an address acknowledge (AACK) signal, which terminates the address bus tenure, the MSC8103 deasserts ABB for a fraction of a bus cycle and then stops driving this pin. The MSC8103 does not assume bus ownership as long as it senses that this pin is asserted by an external bus master. Interrupt Request 21 One of the eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core.
Data Flow
Output Output
IRQ2
Input
Reserved BADDR30
Output Output
IRQ3
Input
Reserved BADDR31
Output Output
IRQ5
Input
BR
Input/Output Output
Input BG Input/Output Output
Input ABB Input/Output Output
Input
IRQ2
Input
1-9
System Bus, HDI16, and Interrupt Signals
Table 1-5.
Signal
TS
System Bus, HDI16, and Interrupt Signals (Continued)
Description
Bus Transfer Start Signals the beginning of a new address bus tenure. The MSC8103 asserts this signal when one of its internal bus masters (SC140 core or DMA) begins an address tenure. When the MSC8103 senses this pin being asserted by an external bus master, it responds to the address bus tenure as required (snoop if enabled, access internal MSC8103 resources, memory controller support). Address Acknowledge A bus slave asserts this signal to indicate that it identified the address tenure. Assertion of this signal terminates the address tenure. Address Retry Assertion of this signal indicates that the bus transaction should be retried by the bus master. The MSC8103 asserts this signal to enforce data coherency with its internal cache and to prevent deadlock situations. Data Bus Grant2 An output when an internal arbiter is used. The MSC8103 asserts this pin as an output to grant data bus ownership to an external bus master. An input when an external arbiter is used. The external arbiter should assert this pin as an input to grant data bus ownership to the MSC8103. Data Bus Busy1 The MSC8103 asserts this pin as an output for the duration of the data bus tenure. Following a TA, which terminates the data bus tenure, the MSC8103 deasserts DBB for a fraction of a bus cycle and then stops driving this pin. The MSC8103 does not assume data bus ownership as long as it senses DBB is asserted by an external bus master. Interrupt Request 31 One of the eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Data Bus Most Significant Word In write transactions the bus master drives the valid data on this bus. In read transactions the slave drives the valid data on this bus. In Host Port Disabled mode, these 32 bits are part of the 64-bit data bus. In Host Port Enabled mode, these bits are used as the bus in 32-bit mode. Data Bus Bits 32-47 In write transactions the bus master drives the valid data on this bus. In read transactions the slave drives the valid data on this bus. Host Data2 When the HDI16 interface is enabled, these signals are lines 0-15 of the bidirectional tri-state data bus. Data Bus Bits 48-51 In write transactions the bus master drives the valid data on these pins. In read transactions the slave drives the valid data on these pins. Host Address Line 0-33 When the HDI16 interface bus is enabled, these lines address internal host registers.
Data Flow
Input/Output
AACK
Input/Output
ARTRY
Input
DBG
Input/Output Output
Input DBB Input/Output Output
Input
IRQ3
Input
D[0-31]
Input/Output
D[32-47]
Input/Output
HD[0-15]
Input/Output
D[48-51]
Input/Output
HA[0-3]
Input
1-10
System Bus, HDI16, and Interrupt Signals
Table 1-5.
Signal
D52
System Bus, HDI16, and Interrupt Signals (Continued)
Description
Data Bus Bit 52 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. Host Chip Select 3 When the HDI16 interface is enabled, this is one of the two chip-select pins. The HDI16 chip select is a logical OR of HCS1 and HCS2. Data Bus Bit 53 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. Host Read Write Select 3 When the HDI16 interface is enabled in Single Strobe mode, this is the read/write input (HRW). Host Read Strobe3 When the HDI16 is programmed to interface with a double data strobe host bus, this pin is the read data strobe Schmitt trigger input (HRD/HRD). The polarity of the data strobe is programmable. Data Bus Bit 54 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. Host Data Strobe3 When the HDI16 is programmed to interface with a single data strobe host bus, this pin is the data strobe Schmitt trigger input (HDS/HDS). The polarity of the data strobe is programmable. Host Write Data Strobe3 When the HDI16 is programmed to interface with a double data strobe host bus, this pin is the write data strobe Schmitt trigger input (HWR/HWR). The polarity of the data strobe is programmable. Data Bus Bit 55 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. Host Request 3 When the HDI16 is programmed to interface with a single host request host bus, this pin is the host request output (HREQ/HREQ). The polarity of the host request is programmable. The host request may be programmed as a driven or open-drain output. Transmit Host Request 3 When the HDI16 is programmed to interface with a double host request host bus, this pin is the transmit host request output (HTRQ/HTRQ). The signal can be programmed as driven or open drain. The polarity of the host request is programmable.
Data Flow
Input/Output
HCS1
Input
D53
Input/Output
HRW
Input
HRD/HRD
Input
D54
Input/Output
HDS/HDS
Input
HWR/HWR
Input
D55
Input/Output
HREQ/HREQ
Output
HTRQ/HTRQ
Output
1-11
System Bus, HDI16, and Interrupt Signals
Table 1-5.
Signal
D56
System Bus, HDI16, and Interrupt Signals (Continued)
Description
Data Bus Bit 56 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. Host Acknowledge3 When the HDI16 is programmed to interface with a single host request host bus, this pin is the host acknowledge Schmitt trigger input (HACK). The polarity of the host acknowledge is programmable. Receive Host Request3 When the HDI16 is programmed to interface with a double host request host bus, this pin is the receive host request output (HRRQ/HRRQ). The signal can be programmed as driven or open drain. The polarity of the host request is programmable. Data Bus Bit 57 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. Host Data Strobe Polarity3 When the HDI16 interface is enabled, this pin is the host data strobe polarity (HDSP). Data Bus Bit 58 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. Host Dual Data Strobe3 When the HDI16 interface is enabled, this pin is the host dual data strobe (HDDS). Data Bus Bit 59 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. H8BIT3 When the HDI16 interface is enabled, this bit determines if the interface is in 8-bit or 16-bit mode. Data Bus Bit 60 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. Host Chip Select 3 When the HDI16 interface is enabled, this is one of the two chip-select pins. The HDI16 chip select is a logical OR of HCS1 and HCS2. Data Bus Bits 61-63 Used only in 60x-mode-only mode. In write transactions the bus master drives the valid data on this bus. In read transactions the slave drives the valid data on this bus. These dedicated signals are reserved when the HDI16 is enabled.3
Data Flow
Input/Output
HACK/HACK
Output
HRRQ/HRRQ
Output
D57
Input/Output
HDSP
Input
D58
Input/Output
HDDS D59
Input Input/Output
H8BIT
Input
D60
Input/Output
HCS2
Input
D[61-63]
Input/Output
Reserved
1-12
System Bus, HDI16, and Interrupt Signals
Table 1-5.
Signal
Reserved DP0
System Bus, HDI16, and Interrupt Signals (Continued)
Description
The primary configuration is reserved. Data Parity 01 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity zero pin should give odd parity (odd number of ones) on the group of signals that includes data parity 0 and D[0-7]. External Bus Request 21,2 An external master asserts this pin to request bus ownership from the internal arbiter. Interrupt Request 11 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Data Parity 11 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity one pin should give odd parity (odd number of ones) on the group of signals that includes data parity 1 and D[8-15]. External Bus Grant 21,2 The MSC8103 asserts this pin to grant bus ownership to an external bus master. Interrupt Request 21 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Data Parity 21 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity two pin should give odd parity (odd number of ones) on the group of signals that includes data parity 2 and D[16-23]. External Data Bus Grant 21,2 The MSC8103 asserts this pin to grant data bus ownership to an external bus master. Interrupt Request 31 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Data Parity 31 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity three pin should give odd parity (odd number of ones) on the group of signals that includes data parity 3 and D[24-31]. External Bus Request 31,2 An external master asserts this pin to request bus ownership from the internal arbiter.
Data Flow
Input Input/Output
EXT_BR2
Input
IRQ1
Input
DP1
Input/Output
EXT_BG2 IRQ2
Output Input
DP2
Input/Output
EXT_DBG2
Output
IRQ3
Input
DP3
Input/Output
EXT_BR3
Input
1-13
System Bus, HDI16, and Interrupt Signals
Table 1-5.
Signal
IRQ4
System Bus, HDI16, and Interrupt Signals (Continued)
Description
Interrupt Request 41 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Data Parity 41 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity four pin should give odd parity (odd number of ones) on the group of signals that includes data parity 4 and D[32-39]. DMA Request 31 An external peripheral uses this pin to request DMA service. External Bus Grant 31,2 The MSC8103 asserts this pin to grant bus ownership to an external bus master. Interrupt Request 51 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Data Parity 51 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity five pin should give odd parity (odd number of ones) on the group of signals that includes data parity 5 and D[40-47]. DMA Request 41 An external peripheral uses this pin to request DMA service. External Data Bus Grant 31,2 The MSC8103 asserts this pin to grant data bus ownership to an external bus master. Interrupt Request 61 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Data Parity 61 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity six pin should give odd parity (odd number of ones) on the group of signals that includes data parity 6 and D[48-55]. DMA Acknowledge 31 The DMA drives this output to acknowledge the DMA transaction on the bus. Interrupt Request 71 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Data Parity 71 The master or slave that drives the data bus also drives the data parity signals. The value driven on the data parity seven pin should give odd parity (odd number of ones) on the group of signals that includes data parity 7 and D[56-63]. DMA Acknowledge1 The DMA drives this output to acknowledge the DMA transaction on the bus. Transfer Acknowledge Indicates that a data beat is valid on the data bus. For single beat transfers, assertion of TA indicates the termination of the transfer. For burst transfers, TA is asserted four times to indicate the transfer of four data beats with the last assertion indicating the termination of the burst transfer.
Data Flow
Input
DP4
Input/Output
DREQ3
Input
EXT_BG3 IRQ5
Output Input
DP5
Input/Output
DREQ4
Input
EXT_DBG3
Output
IRQ6
Input
DP6
Input/Output
DACK3 IRQ7
Output Input
DP7
Input/Output
DACK4 TA
Output Input/Output
1-14
System Bus, HDI16, and Interrupt Signals
Table 1-5.
Signal
TEA
System Bus, HDI16, and Interrupt Signals (Continued)
Description
Transfer Error Acknowledge Indicates a bus error. masters within the MSC8103 monitor the state of this pin. The MSC8103 internal bus monitor can assert this pin if it identifies a bus transfer that is hung. Non-Maskable Interrupt When an external device asserts this line, the MSC8103 NMI input is asserted. Non-Maskable Interrupt Driven from the MSC8103 internal interrupt controller. Assertion of this output indicates that a non-maskable interrupt, pending in the MSC8103 internal interrupt controller, is waiting to be handled by an external host. Data Valid Indicates that a data beat is valid on the data bus. The difference between the TA pin and PSDVAL is that the TA pin is asserted to indicate data transfer terminations while the PSDVAL signal is asserted with each data beat movement. Thus, when TA is asserted, PSDVAL is asserted, but when PSDVAL is asserted, TA is not necessarily asserted. For example when the SDMA initiates a double word (2x64 bits) transfer to a memory device that has a 32-bit port size, PSDVAL is asserted three times without TA, and finally both pins are asserted to terminate the transfer. Interrupt Request 71 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Interrupt Output1 Driven from the MSC8103 internal interrupt controller. Assertion of this output indicates that an unmasked interrupt is pending in the MSC8103 internal interrupt controller.
Data Flow
Input/Output
NMI NMI_OUT
Input Output
PSDVAL
Input/Output
IRQ7
Input
INT_OUT
Output
Notes:
1. 2.
3.
See the System Interface Unit (SIU) chapter in the MCS8103 Reference Manual for details on how to configure these pins. When used as the bus control arbiter for the system bus, the MSC8103 can support up to three external bus masters. Each master uses its own set of Bus Request, Bus Grant, and Data Bus Grant signals (BR/BG/DBG, EXT_BR2/EXT_BG2/EXT_DBG2, and EXT_BR3/EXT_BG3/EXT_DBG3). Each of these signal sets must be configured to indicate whether the external master is or is not a MSC8103 master device. See the Bus Configuration Register (BCR) description in the System Interface Unit (SIU) chapter in the MCS8103 Reference Manual for details on how to configure these pins. The second and third set of pins is defined by EXT_xxx to indicate that they can only be used with external master devices. The first set of pins (BR/BG/DBG) have a dual function. When the MSC8103 is not the bus arbiter, these signals (BR/BG/DBG) are used by the MSC8103 to obtain master control of the bus. See the Host Interface (HDI16) chapter in the MCS8103 Reference Manual for details on how to configure these pins.
1-15
Memory Controller Signals
1.6 Memory Controller Signals
Refer to the Memory Controller chapter in the MSC8103 Reference Manual (MSC8103RM/D) for detailed information about configuring these signals. Table 1-6. Memory Controller Signals
Signal
CS[0-7] BCTL1
Data Flow
Output Output
Description
Chip Select Enable specific memory devices or peripherals connected to MSC8103 buses. Buffer Control 1 Controls buffers on the data bus. Usually used with BCTL0. The exact function of this pin is defined by the value of SIUMCR[BCTLC]. See the System Interface Unit (SIU) chapter in the MS8103 Technical Reference manual for details. Burst Address 27-28 Two of five outputs of the memory controller. These pins connect directly to memory devices controlled by the MSC8103 memory controller. Address Latch Enable Controls the external address latch used in external master bus configuration. Buffer Control 0 Controls buffers on the data bus. The exact function of this pin is defined by the value of SIUMCR[BCTLC]. See the System Interface Unit (SIU) chapter in the MS8103 Technical Reference manual for details. Bus Write Enable Outputs of the bus General-Purpose Chip-select Machine (GPCM). These pins select byte lanes for write operations. Bus SDRAM DQM Outputs of the SDRAM control machine. These pins select specific byte lanes of SDRAM devices. Bus UPM Byte Select Outputs of the User-Programmable Machine (UPM) in the memory controller. These pins select specific byte lanes during memory operations. The timing of these pins is programmed in the UPM. The actual driven value depends on the address and size of the transaction and the port size of the accessed device. Bus SDRAM A10 Output from the bus SDRAM controller. This pin is part of the address when a row address is driven. It is part of the command when a column address is driven. Bus UPM General-Purpose Line 0 One of six general-purpose output lines of the UPM. The values and timing of this pin are programmed in the UPM. Bus SDRAM Write Enable Output from the bus SDRAM controller. This pin should connect to the SDRAM WE input signal. Bus UPM General-Purpose Line 1 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM.
BADDR[27-28]
Output
ALE BCTL0
Output Output
PWE[0-7]
Output
PSDDQM[0-7]
Output
PBS[0-7]
Output
PSDA10
Output
PGPL0
Output
PSDWE
Output
PGPL1
Output
1-16
Memory Controller Signals
Table 1-6. Memory Controller Signals (Continued)
Signal
POE
Data Flow
Output
Description
Bus Output Enable Output of the bus GPCM. Controls the output buffer of memory devices during read operations. Bus SDRAM RAS Output from the bus SDRAM controller. This pin should connect to the SDRAM Row Address Strobe (RAS) input signal. Bus UPM General-Purpose Line 2 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. Bus SDRAM CAS Output from the bus SDRAM controller. This pin should connect to the SDRAM Column Address Strobe (CAS) input signal. Bus UPM General-Purpose Line 3 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. GPCM TA Terminates transactions during GPCM operation. Requires an external pull up resistor for proper operation. Bus UPM Wait Input to the UPM. An external device can hold this pin high to force the UPM to wait until the device is ready for the operation to continue. Bus Parity Byte Select In systems in which data parity is stored in a separate chip, this output is the byte-select for that chip. Bus UPM General-Purpose Line 4 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. Bus SDRAM Address Multiplexer Controls the SDRAM address multiplexer when the MSC8103 is in External Master mode. Bus UPM General-Purpose Line 5 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM.
PSDRAS
Output
PGPL2
Output
PSDCAS
Output
PGPL3
Output
PGTA
Input
PUPMWAIT
Input
PPBS
Output
PGPL4
Output
PSDAMUX
Output
PGPL5
Output
1-17
Communications Processor Module (CPM) Ports
1.7 Communications Processor Module (CPM) Ports
The MSC8103 CPM supports a subset of signals included in the MPC8260. The following sections describe the functionality of the signals in the MSC8103. * The MSC8103 CPM includes the following set of communication controllers: * Two full-duplex Fast Serial Communications Controllers (FCCs) that support: -- Asynchronous Transfer Mode (ATM) through a UTOPIA 8 interface (FCC1 only)--The MSC8103 can operate as one of the following: UTOPIA slave device UTOPIA multi-PHY master device using direct polling for up to 4 PHY devices UTOPIA multi-PHY master device using multiplex polling that can address up to 31 PHY devices at addresses 0-30 (address 31 is reserved as a null port). -- IEEE 802.3/Fast Ethernet through a Media-Independent Interface (MII) -- High-Level Data Link Control (HDLC) Protocol: Serial mode--Transfers data one bit at a time Nibble mode--Transfers data four bits at a time -- Transparent mode serial operation * One FCC that operates with the TSA only * Two Multi-Channel Controllers (MCCs) that together can handle up to 256 HDLC/transparent channels at 64 Kbps each, multiplexed on up to four TDM interfaces * Two full-duplex serial communications controllers (SCCs) that support the following protocols: -- IEEE 802.3/Fast Ethernet through a Media-Independent Interface (MII) -- HDLC Protocol: Serial mode--Transfers data one bit at a time Nibble mode--Transfers data four bits at a time -- Synchronous Data Link Control (SDLC) -- LocalTalk (HDLC-based local area network protocol) -- Universal Asynchronous Receiver/Transmitter (UART) -- Synchronous UART (1x clock mode) -- Binary Synchronous (BISYNC) communication -- Transparent mode serial operation * Two additional SCCs that operate with the TSA only * Two full-duplex Serial Management Controllers (SMCs) that support the following protocols: -- General Circuit Interface (GCI)/Integrated Services Digital Network (ISDN) monitor and C/I channels (TSA only) -- UART -- Transparent mode serial operation * Serial Peripheral Interface (SPI) support for master or slave operation * Inter-Integrated Circuit (I2C) bus controller * Time-Slot Assigner (TSA) that supports multiplexing from any of the SCCs, FCCs, SMCs, and two MCCs onto four time-division multiplexed (TDM) interfaces. The TSA uses two Serial Interfaces (SI1 and SI2). SI1 uses TDMA1 which supports both serial and nibble mode. SI2 does not support nibble mode and includes TDMB2, TDMC2, and TDMD2 which operate only in serial mode. The individual sets of externals signals associated with a specific protocol and data transfer mode are multiplexed across any or all of the ports, as shown in Figure 1-2. The following sections provide detailed descriptions of the signals supported by Ports A-Port D.
1-18
Communications Processor Module (CPM) Ports
1.7.1 Port A Signals
Table 1-7. Port A Signals
Name GeneralPurpose I/O
PA31
Peripheral Controller: Dedicated Signal Protocol
FCC1: TXENB UTOPIA master
Dedicated I/O Data Direction
Output
Description
FCC1: UTOPIA Master Transmit Enable In the ATM UTOPIA interface supported by FCC1, TXENB is asserted by the MSC8103 (UTOPIA master PHY) when there is valid transmit cell data (TXD[0-7]). FCC1: UTOPIA Slave Transmit Enable In the ATM UTOPIA interface supported by FCC1, TXENB is asserted by an external UTOPIA master PHY when there is valid transmit cell data (TXD[0-7]). FCC1: Media Independent Interface Collision Detect In the MII interface supported by FCC1, COL is asserted by an external fast Ethernet PHY. FCC1: UTOPIA Slave Transmit Cell Available In the ATM UTOPIA interface supported by FCC1, TXCLAV is asserted by the MSC8103 (UTOPIA slave PHY) when the MSC8103 can accept one complete ATM cell. FCC1: UTOPIA Master Transmit Cell Available In the ATM UTOPIA interface supported by FCC1, TXCLAV is asserted by an external UTOPIA slave PHY to indicate that it can accept one complete ATM cell. FCC1: UTOPIA Master Transmit Cell Available Multi-PHY Direct Polling In the ATM UTOPIA interface supported by FCC1, TXCLAV0 is asserted by an external UTOPIA slave PHY using direct polling to indicate that it can accept one complete ATM cell. FCC1: Request To Send In the standard modem interface signals supported by FCC1 (RTS, CTS, and CD). RTS is asynchronous with the data. RTS is typically used in conjunction with CD. The MSC8103 FCC1 transmitter requests the receiver to send data by asserting RTS low. The request is accepted when CTS is returned low. FCC1: Media Independent Interface Carrier Sense In the MII interface supported by FCC1. CRS is asserted by an external fast Ethernet PHY. It indicates activity on the cable. FCC1: UTOPIA Transmit Start of Cell In the ATM UTOPIA interface supported by FCC1. TXSOC is asserted by the MSC8103 (UTOPIA master PHY) when TXD[0-7] contains the first valid byte of the cell. FCC1: Media Independent Interface Transmit Error In the MII interface supported by FCC1. TX_ER is asserted by the MSC8103 to force propagation of transmit errors.
FCC1: TXENB UTOPIA slave
Input
FCC1: COL MII PA30 FCC1: TXCLAV UTOPIA slave
Input
Output
FCC1: TXCLAV UTOPIA master, or
Input
FCC1: TXCLAV0 UTOPIA master, Multi-PHY, direct polling
Input
FCC1: RTS HDLC, Serial and Nibble
Output
FCC1: CRS MII
Input
PA29
FCC1: TXSOC UTOPIA master
Output
FCC1: TX_ER MII
Output
1-19
Communications Processor Module (CPM) Ports
Table 1-7. Port A Signals (Continued)
Name GeneralPurpose I/O
PA28
Peripheral Controller: Dedicated Signal Protocol
FCC1: RXENB UTOPIA master
Dedicated I/O Data Direction
Output
Description
FCC1: UTOPIA Master Receive Enable In the ATM UTOPIA interface supported by FCC1. (UTOPIA master) RXENB is asserted by the MSC8103 (UTOPIA master PHY) to indicate that RXD[0-7] and RXSOC are to be sampled at the end of the next cycle. RXD[0-7] and RXSOC are enabled only in cycles following those with RXENB asserted. FCC1: UTOPIA Master Receive Enable In the ATM UTOPIA interface supported by FCC1. (UTOPIA slave) RXENB is an input asserted by an external PHY to indicate that RXD[0-7] and RXSOC is to be sampled at the end of the next cycle. RXD[0-7] and RXSOC are enabled only in cycles following those with RXENB asserted. FCC1: Media Independent Interface Transmit Enable In the MII interface supported by FCC1. TX_EN is asserted by the MSC8103 when transmitting data. FCC1: UTOPIA Receive Start of Cell Asserted by the MSC8103 (UTOPIA slave) for an external PHY when RXD[0-7] contains the first valid byte of the cell. FCC1: Media Independent Interface Receive Data Valid In the MII interface supported by FCC1. RX_DV is an input asserted by an external fast Ethernet PHY. RX_DV indicates that valid data is being sent. The presence of carrier sense but not RX_DV indicates reception of broken packet headers, probably due to bad wiring or a bad circuit. FCC1: UTOPIA Slave Receive Cell Available In the ATM UTOPIA interface supported by FCC1. RXCLAV is asserted by the MSC8103 (UTOPIA slave PHY) when one complete ATM cell is available for transfer. FCC1: UTOPIA Master Receive Cell Available In the ATM UTOPIA interface supported by FCC1. RXCLAV is asserted by an external PHY when one complete ATM cell is available for transfer. FCC1: UTOPIA Master Receive Cell Available 0 Direct Polling In the ATM UTOPIA interface supported by FCC1, RXCLAV0 is asserted by an external PHY when one complete ATM cell is available for transfer. FCC1: Media Independent Interface Receive Error In the MII interface and supported by FCC1. RX_ER is asserted by an external fast Ethernet PHY. This signal indicates a receive error, which often indicates bad wiring.
FCC1: RXENB UTOPIA slave
Input
FCC1: TX_EN MII PA27 FCC1: RXSOC UTOPIA slave
Output
Output
FCC1: RX_DV MII
Input
PA26
FCC1: RXCLAV UTOPIA slave
Output
FCC1: RXCLAV UTOPIA master, or
Input
RXCLAV0 UTOPIA master, Multi-PHY, direct polling
Input
FCC1: RX_ER MII
Input
1-20
Communications Processor Module (CPM) Ports
Table 1-7. Port A Signals (Continued)
Name GeneralPurpose I/O
PA25
Peripheral Controller: Dedicated Signal Protocol
FCC1: TXD0 UTOPIA
Dedicated I/O Data Direction
Output
Description
FCC1: UTOPIA Transmit Data Bit 0 In the ATM UTOPIA interface supported by FCC1. The MSC8103 outputs ATM cell octets (UTOPIA interface data) on TXD[0-7]. TXD7 is the most significant bit. TXD0 is the least significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. Module Serial Number Bit 0 MSNUM[0-4] of is the sub-block code of the current peripheral controller using SDMA. MSNUM5 indicates which section, transmit (0) or receive (1), is active during the transfer. FCC1: UTOPIA Transmit Data Bit 1 In the ATM UTOPIA interface supported by FCC1. The MSC8103 outputs ATM cell octets (UTOPIA interface data) on TXD[0-7]. TXD7 is the most significant bit. TXD0 is the least significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. Module Serial Number Bit 1 MSNUM[0-4] of is the sub-block code of the current peripheral controller using SDMA. MSNUM5 indicates which section, transmit (0) or receive (1), is active during the transfer. FCC1: UTOPIA Transmit Data Bit 2 TXD[0-7] is part of the ATM UTOPIA interface supported by FCC1. The MSC8103 outputs ATM cell octets (UTOPIA interface data) on TXD[0-7]. TXD7 is the most significant bit. TXD0 is the least significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. FCC1: UTOPIA Transmit Data Bit 3 TXD[0-7] is part of the ATM UTOPIA interface supported by FCC1. The MSC8103 outputs ATM cell octets (UTOPIA interface data) on TXD[0-7]. TXD7 is the most significant bit. TXD0 is the least significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. FCC1: UTOPIA Transmit Data Bit 4 TXD[0-7] is part of the ATM UTOPIA interface supported by FCC1. The MSC8103 outputs ATM cell octets (UTOPIA interface data) on TXD[0-7]. TXD7 is the most significant bit. TXD0 is the least significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. FCC1: MII and HDLC Nibble Transmit Data Bit 3 TXD[3-0] supports MII and HDLC nibble modes in FCC1. TXD3 is the most significant bit. TXD0 is the least significant bit.
SDMA: MSNUM0
Output
PA24
FCC1: TXD1 UTOPIA
Output
SDMA: MSNUM1
Output
PA23
FCC1: TXD2 UTOPIA
Output
PA22
FCC1: TXD3 UTOPIA
Output
PA21
FCC1: TXD4 UTOPIA
Output
FCC1: TXD3 MII and HDLC nibble
Output
1-21
Communications Processor Module (CPM) Ports
Table 1-7. Port A Signals (Continued)
Name GeneralPurpose I/O
PA20
Peripheral Controller: Dedicated Signal Protocol
FCC1: TXD5 UTOPIA
Dedicated I/O Data Direction
Output
Description
FCC1: UTOPIA Transmit Data Bit 5 TXD[0-7] is part of the ATM UTOPIA interface supported by FCC1. The MSC8103 outputs ATM cell octets (UTOPIA interface data) on TXD[0-7]. TXD7 is the most significant bit. TXD0 is the least significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. FCC1: MII and HDLC Nibble Transmit Data Bit 2 TXD[3-0] is supported by MII and HDLC nibble modes in FCC1. TXD3 is the most significant bit. TXD0 is the least significant bit. FCC1: UTOPIA Transmit Data Bit 6 TXD[0-7] is part of the ATM UTOPIA interface supported by FCC1. The MSC8103 outputs ATM cell octets (UTOPIA interface data) on TXD[0-7]. TXD7 is the most significant bit. TXD0 is the least significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. FCC1: MII and HDLC Nibble Transmit Data Bit 1 TXD[3-0] is supported by MII and HDLC transparent nibble modes in FCC1. TXD3 is the most significant bit. TXD0 is the least significant bit. FCC1: UTOPIA Transmit Data Bit 7. TXD[0-7] is part of the ATM UTOPIA interface supported by FCC1. The MSC8103 outputs ATM cell octets (UTOPIA interface data) on TXD[0-7]. TXD7 is the most significant bit. TXD0 is the least significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. FCC1: MII and HDLC Nibble Transmit Data Bit 0 TXD[3-0] is supported by MII and HDLC nibble modes in FCC1. TXD3 is the most significant bit. TXD0 is the least significant bit. FCC1: HDLC Serial and Transparent Transmit Data Bit The TXD serial bit is supported by HDLC serial and transparent modes in FCC1. FCC1: UTOPIA Receive Data Bit 7. RXD[0-7] is part of the ATM UTOPIA interface supported by FCC1. The MSC8103 inputs ATM cell octets (UTOPIA interface data) on RXD[0-7]. RXD7 is the most significant bit. RXD0 is the least significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0-7] is tri-stated, enabled only when RXENB is asserted. FCC1: MII and HDLC Nibble Receive Data Bit 0 RXD[3-0] is supported by MII and HDLC nibble mode in FCC1. RXD3 is the most significant bit. RXD0 is the least significant bit. FCC1: HDLC Serial and Transparent Receive Data Bit The RXD serial bit is supported by HDLC and transparent by FCC1.
FCC1: TXD2 MII and HDLC nibble
Output
PA19
FCC1: TXD6 UTOPIA
Output
FCC1: TXD1 MII and HDLC nibble
Output
PA18
FCC1: TXD7 UTOPIA
Output
FCC1: TXD0 MII and HDLC nibble
Output
FCC1: TXD HDLC serial and transparent PA17 FCC1: RXD7 UTOPIA
Output
Input
FCC1: RXD0 MII and HDLC nibble
Input
FCC1: RXD HDLC serial and transparent
Input
1-22
Communications Processor Module (CPM) Ports
Table 1-7. Port A Signals (Continued)
Name GeneralPurpose I/O
PA16
Peripheral Controller: Dedicated Signal Protocol
FCC1: RXD6 UTOPIA
Dedicated I/O Data Direction
Input
Description
FCC1: UTOPIA Receive Data Bit 6. RXD[0-7] is part of the ATM UTOPIA interface supported by FCC1. The MSC8103 inputs ATM cell octets (UTOPIA interface data) on RXD[0-7]. RXD7 is the most significant bit. RXD0 is the least significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0-7] is tri-stated, enabled only when RXENB is asserted. FCC1: MII and HDLC Nibble Receive Data Bit 1 RXD[3-0] is supported by MII and HDLC nibble mode in FCC1. RXD3 is the most significant bit. RXD0 is the least significant bit. FCC1: UTOPIA Receive Data Bit 5 In the ATM UTOPIA interface supported by FCC1. The MSC8103 inputs ATM cell octets (UTOPIA interface data) on RXD[0-7]. RXD7 is the most significant bit. RXD0 is the least significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0-7] is tri-stated, enabled only when RXENB is asserted. FCC1: MII and HDLC Nibble Receive Data Bit 2 RXD[3-0] is supported by MII and HDLC nibble mode in FCC1. RXD3 is the most significant bit. RXD0 is the least significant bit. FCC1: UTOPIA Receive Data Bit 4. In the ATM UTOPIA interface supported by FCC1. The MSC8103 inputs ATM cell octets (UTOPIA interface data) on RXD[0-7]. RXD7 is the most significant bit. RXD0 is the least significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0-7] is tri-stated, enabled only when RXENB is asserted. FCC1: MII and HDLC Nibble Receive Data Bit 3 RXD[3-0] is supported by MII and HDLC nibble mode in FCC1. RXD3 is the most significant bit. RXD0 is the least significant bit. FCC1: UTOPIA Receive Data Bit 3 In the ATM UTOPIA interface supported by FCC1. The MSC8103 inputs ATM cell octets (UTOPIA interface data) on RXD[0-7]. RXD7 is the most significant bit. RXD0 is the least significant bit. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0-7] is tri-stated, enabled only when RXENB is asserted. Module Serial Number Bit 2 MSNUM[0-4] is the sub-block code of the current peripheral controller using SDMA. MSNUM5 indicates which section, transmit (0) or receive (1), is active during the transfer.
FCC1: RXD1 MII and HDLC nibble
Input
PA15
FCC1: RXD5 UTOPIA
Input
RXD2 MII and HDLC nibble
Input
PA14
FCC1: RXD4 UTOPIA
Input
FCC1: RXD3 MII and HDLC nibble
Input
PA13
FCC1: RXD3 UTOPIA
Input
SDMA: MSNUM2
Output
1-23
Communications Processor Module (CPM) Ports
Table 1-7. Port A Signals (Continued)
Name GeneralPurpose I/O
PA12
Peripheral Controller: Dedicated Signal Protocol
FCC1: RXD2 UTOPIA
Dedicated I/O Data Direction
Input
Description
FCC1: UTOPIA Receive Data Bit 2 In the ATM UTOPIA interface supported by FCC1. The MSC8103 inputs ATM cell octets (UTOPIA interface data) on RXD[0-7]. RXD7 is the most significant bit. RXD0 is the least significant bit. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0-7] is tri-stated, enabled only when RXENB is asserted. Module Serial Number Bit 3 MSNUM[0-4] of is the sub-block code of the current peripheral controller using SDMA. MSNUM5 indicates which section, transmit (0) or receive (1), is active during the transfer. FCC1: UTOPIA RX Receive Data Bit 1 In the ATM UTOPIA interface supported by FCC1. The MSC8103 inputs ATM cell octets (UTOPIA interface data) on RXD[0-7]. RXD7 is the most significant bit. RXD0 is the least significant bit. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0-7] is tri-stated, enabled only when RXENB is asserted. Module Serial Number Bit 4 MSNUM[0-4] of is the sub-block code of the current peripheral controller using SDMA. MSNUM5 indicates which section, transmit (0) or receive (1) is active during the transfer. FCC1: UTOPIA RX Receive Data Bit 0 In the ATM UTOPIA interface supported by FCC1. The MSC8103 inputs ATM cell octets (UTOPIA interface data) on RXD[0-7]. RXD7 is the most significant bit. RXD0 is the least significant bit. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0-7] is tri-stated, enabled only when RXENB is asserted. Module Serial Number Bit 5 MSNUM[0-4] of is the sub-block code of the current peripheral controller using SDMA. MSNUM5 indicates which section, transmit (0) or receive (1), is active during the transfer. SMC2: Serial Management Transmit Data Supported by SMC2. The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock. Not all signals are used for all applications. SMCs are full-duplex ports that supports three protocols or modes: UART, transparent, or general-circuit interface (GCI). See also PC15. Time-Division Multiplexing A1: Layer 1 Transmit Data Bit 0 In the TDMA1 interface supported by SI1. L1TXD3 is the most significant bit. L1TXD0 is the least significant bit in nibble mode. TDMA1 transmits nibble data out L1TXD[0-3].
SDMA: MSNUM3
Output
PA11
FCC1: RXD1 UTOPIA
Input
SDMA: MSNUM4
Output
PA10
FCC1: RXD0 UTOPIA
Input
SDMA: MSNUM5
Output
PA9
SMC2: SMTXD
Output
SI1 TDMA1: L1TXD0 TDM nibble
Output
1-24
Communications Processor Module (CPM) Ports
Table 1-7. Port A Signals (Continued)
Name GeneralPurpose I/O
PA8
Peripheral Controller: Dedicated Signal Protocol
SMC2: SMRXD
Dedicated I/O Data Direction
Input
Description
SMC2: Serial Management Receive Data Supported by SMC2. The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock. Not all signals are used for all applications. SMCs are full-duplex ports that supports three protocols or modes: UART, transparent, or general-circuit interface (GCI). Time-Division Multiplexing A1: Layer 1 Nibble Receive Data Bit 0 In the TDMA1 interface supported by SI1. L1RXD3 is the most significant bit. L1RXD0 is the least significant bit in nibble mode. TDMA1 receives nibble data from L1RXD[0-3]. Time-Division Multiplexing A1: Layer 1 Serial Receive Data In the TDMA1 interface supported by SI1. TDMA1 receives serial data from L1RXD. SMC2: Serial Management Synchronization The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock. Not all signals are used for all applications. SMCs are full-duplex ports that supports three protocols or modes: UART, transparent, or general-circuit interface (GCI). Time-Division Multiplexing A1: Layer 1 Transmit Synchronization In the TDMA1 interface supported by SI1, this is the synchronizing signal for the transmit channel. See the Serial Interface with Time-Slot Assigner chapter in the MSC8103 Technical Reference manual. Time-Division Multiplexing A1: Layer 1 Receive Synchronization. In the TDMA1 interface supported by SI1, this is the synchronizing signal for the receive channel.
SI1 TDMA1: L1RXD0 TDM nibble
Input
SI1 TDMA1: L1RXD TDM serial
Input
PA7
SMC2: SMSYN
Input
SI1 TDMA1: L1TSYNC TDM nibble and TDM serial
Input
PA6
SI1 TDMA1: L1RSYNC TDM nibble and TDM serial
Input
1-25
Communications Processor Module (CPM) Ports
1.7.2 Port B Signals
Table 1-8. Port B Signals
Name GeneralPurpose I/O
PB31
Peripheral Controller: Dedicated I/O Protocol
FCC2: TX_ER MII
Dedicated I/O Data Direction
Output
Description
FCC2: Media Independent Interface Transmit Error In the MII interface supported by FCC2. TX_ER is asserted by the MSC8103 to force propagation of transmit errors. SCC2: Receive Data Supported by SCC2. SCC2 receives serial data from RXD. Time-Division Multiplexing B2: Layer 1 Transmit Data In the TDMB2 interface supported by SI2. L1TXD supports serial mode. TDMB2 transmits serial data out of L1TXD. SCC2: Transmit Data. Supported by SCC2. SCC2 transmits serial data out of TXD. FCC2: Media Independent Interface Receive Data Valid In the MII interface supported by FCC2, RX_DV is asserted by an external fast Ethernet PHY. RX_DV indicates that valid data is being sent. The presence of carrier sense, but not RX_DV, indicates reception of broken packet headers, probably due to bad wiring or a bad circuit. Time-Division Multiplexing B2: Layer 1 Receive Data In the TDMB2 interface supported by SI2. L1RXD supports serial mode. TDMB2 receives serial data from L1RXD. FCC2: Media Independent Interface Transmit Enable In the MII interface supported by FCC2. TX_EN is asserted by the MSC8103 when transmitting data. Time-Division Multiplexing B2: Layer 1 Receive Synchronization In the TDMB2 interface supported by SI2, this is the synchronizing signal for the receive channel.
SCC2: RXD
Input
SI2 TDMB2: L1TXD TDM serial PB30 SCC2: TXD
Output
Output
FCC2: RX_DV MII
Input
SI2 TDMB2: L1RXD TDM serial PB29 FCC2: TX_EN MII
Input Output
SI2 TDMB2: L1RSYNC TDM serial
Input
1-26
Communications Processor Module (CPM) Ports
Table 1-8. Port B Signals (Continued)
Name GeneralPurpose I/O
PB28
Peripheral Controller: Dedicated I/O Protocol
FCC2: RTS HDLC serial, HDLC nibble, and transparent
Dedicated I/O Data Direction
Output
Description
FCC2: Request to Send One of the standard modem interface signals supported by FCC2 (RTS, CTS, and CD). RTS is asynchronous with the data. RTS is typically used in conjunction with CD. The MSC8103 FCC2 transmitter requests the receiver to send data by asserting RTS low. The request is accepted when CTS is returned low. FCC2: Media Independent Interface Receive Error In the MII interface supported by FCC2, RX_ER is asserted by an external fast Ethernet PHY. This signal indicates a receive error, which often indicates bad wiring. SCC2: Request to Send, Transmit Enable Typically used in conjunction with CD supported by SCC2. The MSC8103 SCC2 transmitter requests the receiver to send data by asserting RTS low. The request is accepted when CTS is returned low. TENA is the signal used in Ethernet mode. Time-Division Multiplexing B2: Layer 1 Transmit Synchronization In the TDMB2 interface supported by SI2, this is the synchronizing signal for the transmit channel. See the Serial Interface with Time-Slot Assigner chapter in the MSC8103 Technical Reference manual. FCC2: Media Independent Interface Collision Detect In the MII interface supported by FCC2. COL is asserted by an external fast Ethernet PHY. Time-Division Multiplexing C2: Layer 1 Transmit Data In the TDMC2 interface supported by SI2. L1TXD supports serial mode. TDMC2 transmits serial data out of L1TXD. FCC2: Media Independent Interface Carrier Sense Input In the MII interface, CRS is asserted by an external fast Ethernet PHY. This signal indicates activity on the cable. Time-Division Multiplexing C2: Layer 1 Receive Data In the TDMC2 interface supported by SI2. L1RXD supports serial mode. TDMC2 receives serial data from L1RXD.
FCC2: RX_ER MII
Input
SCC2: RTS, TENA
Output
SI2 TDMB2: L1TSYNC TDM serial
Input
PB27
FCC2: COL MII
Input
SI2 TDMC2: L1TXD TDM serial PB26 FCC2: CRS MII
Output
Input
SI2 TDMC2: L1RXD TDM serial
Input
1-27
Communications Processor Module (CPM) Ports
Table 1-8. Port B Signals (Continued)
Name GeneralPurpose I/O
PB25
Peripheral Controller: Dedicated I/O Protocol
FCC2: TXD3 MII and HDLC nibble
Dedicated I/O Data Direction
Output
Description
FCC2: MII and HDLC Nibble Transmit Data Bit 3 Supported by MII and HDLC nibble mode in FCC2. TXD3 is the most significant bit. TXD0 is the least significant bit. Time-Division Multiplexing A1: Nibble Layer 1 Transmit Data Bit 3 TDMA1 transmits nibble data out of L1TXD[0-3]. L1TXD3 is the most significant bit and L1TXD0 is the least significant bit in nibble mode. Time-Division Multiplexing C2: Layer 1 Transmit Synchronization In the TDMC2 interface supported by SI2, this is the synchronizing signal for the transmit channel. See the Serial Interface with Time-Slot Assigner chapter in the MSC8103 Technical Reference manual. FCC2: MII and HDLC Nibble: Transmit Data Bit 2 Supported by MII and HDLC nibble mode in FCC2. TXD3 is the most significant bit. TXD0 is the least significant bit. Time-Division Multiplexing A1: Nibble Layer 1 Receive Data Bit 3 TDMA1 receives nibble data into L1RXD[0-3]. L1RXD3 is the most significant bit and L1RXD0 is the least significant bit in nibble mode. Time-Division Multiplexing C2: Layer 1 Receive Synchronization In the TDMC2 interface supported by SI2, this is the synchronizing signal for the receive channel. FCC2: MII and HDLC Nibble: Transmit Data Bit 1 Supported by MII and HDLC nibble mode in FCC2. TXD3 is the most significant bit. TXD0 is the least significant bit. Time-Division Multiplexing A1: Nibble Layer 1 Receive Data Bit 2 In the TDMA1 interface supported by SI1. TDMA1 supports bit and nibble modes. L1RXD3 is the most significant bit. L1RXD0 is the least significant bit in nibble mode. TDMA1 receives nibble data from L1RXD[0-3]. Time-Division Multiplexing D2: Layer 1 Transmit Data In the TDMD2 interface supported by SI2. L1TXD supports serial mode. TDMA1 transmits serial data out of L1TXD.
SI1 TDMA1: L1TXD3 TDM nibble
Output
SI2 TDMC2: L1TSYNC TDM serial
Input
PB24
FCC2: TXD2 MII and HDLC nibble
Output
SI1 TDMA1: L1RXD3 nibble
Input
SI2 TDMC2: L1RSYNC serial
Input
PB23
FCC2: TXD1 MII and HDLC nibble
Output
SI1 TDMA1: L1RXD2 TDM nibble
Input
SI2 TDMD2: L1TXD TDM serial
Output
1-28
Communications Processor Module (CPM) Ports
Table 1-8. Port B Signals (Continued)
Name GeneralPurpose I/O
PB22
Peripheral Controller: Dedicated I/O Protocol
FCC2: TXD0 MII and HDLC nibble
Dedicated I/O Data Direction
Output
Description
FCC2: MII and HDLC Nibble Transmit Data Bit 0 TXD[0-3] is supported by MII and HDLC nibble mode in FCC2. TXD3 is the most significant bit. TXD0 is the least significant bit. FCC2: HDLC Serial and Transparent Transmit Data TXD is supported by HDLC serial mode and transparent mode in FCC2. Time-Division Multiplexing A1: Nibble Layer 1 Receive Data Bit 1 In the TDMA1 interface supported by SI1. TDMA1 supports bit and nibble modes. L1RXD3 is the most significant bit. L1RXD0 is the least significant bit in nibble mode. TDMA1 receives nibble data from L1RXD[0-3]. Time-Division Multiplexing D2: Layer 1 Receive Data In the TDMD2 interface supported by SI2. TDMD2 supports serial mode. TDMD2 receives serial data from L1RXD. FCC2: MII and HDLC Nibble Receive Data Bit 0 RXD[0-3] is supported by MII and HDLC nibble mode in FCC2. RXD3 is the most significant bit. RXD0 is the least significant bit. FCC2: HDLC Serial and Transparent Receive Data Supported by HDLC serial mode and transparent mode in FCC2. Time-Division Multiplexing A1: Nibble Layer 1 Transmit Data Bit 2 In the TDMA1 interface supported by SI1. TDMA1 supports bit and nibble modes. L1TXD3 is the most significant bit. L1TXD0 is the least significant bit in nibble mode. TDMA1 transmits nibble data out of L1TXD[0-3]. Time-Division Multiplexing D2: Layer 1 Transmit Synchronize Data In the TDMD2 interface supported by SI2, this is the synchronizing signal for the transmit channel. See the Serial Interface with Time-Slot Assigner chapter in the MSC8103 Technical Reference manual.
FCC2: TXD HDLC serial and transparent
Output
SI1 TDMA1: L1RXD1 TDM nibble
Input
SI2 TDMD2: L1RXD TDM serial PB21 FCC2: RXD0 MII and HDLC nibble
Input
Input
FCC2: RXD HDLC serial and transparent
Input
SI1 TDMA1: L1TXD2 TDM nibble
Output
SI2 TDMD2: L1TSYNC TDM serial
Input
1-29
Communications Processor Module (CPM) Ports
Table 1-8. Port B Signals (Continued)
Name GeneralPurpose I/O
PB20
Peripheral Controller: Dedicated I/O Protocol
FCC2: RXD1 MII and HDLC nibble
Dedicated I/O Data Direction
Input
Description
FCC2: MII and HDLC Nibble: Receive Data Bit 1 RXD[0-3] is supported by MII and HDLC nibble mode in FCC2. RXD3 is the most significant bit. RXD0 is the least significant bit. Time-Division Multiplexing A1: Nibble Layer 1 Transmit Data Bit 1 In the TDMA1 interface supported by SI1. TDMA1 supports bit and nibble modes. L1TXD3 is the most significant bit. L1TXD0 is the least significant bit in nibble mode. TDMA1 transmits nibble data out of L1TXD[0-3]. Time-Division Multiplexing D2: Layer 1 Receive Synchronize Data In the TDMD2 interface supported by SI2, this is the synchronizing signal for the receive channel. FCC2: MII and HDLC Nibble Receive Data Bit 2 RXD[0-3] is supported by MII and HDLC nibble mode in FCC2. RXD3 is the most significant bit. RXD0 is the least significant bit. I2C: Inter-Integrated Circuit Serial Data The I2C interface comprises two signals: serial data (SDA) and serial clock (SDA). The I2C controller uses a synchronous, multimaster bus that can connect several integrated circuits on a board. Clock rates run up to 520 kHz@25 MHz system clock. FCC2: MII and HDLC Nibble Receive Data Bit 3 RXD[0-3] is supported by MII and HDLC nibble mode in FCC2. RXD3 is the most significant bit. RXD0 is the least significant bit. I2C: Inter-Integrated Circuit Serial Clock The I2C interface comprises two signals: serial data (SDA) and serial clock (SDA). The I2C controller uses a synchronous, multimaster bus that can connect several integrated circuits on a board. Clock rates run up to 520 kHz@25 MHz system clock.
SI1 TDMA1: L1TXD1 TDM nibble
Output
SI2 TDMD2: L1RSYNC TDM serial
Input
PB19
FCC2: RXD2 MII and HDLC nibble
Input
I2C: SDA
Input/ Output
PB18
FCC2: RXD3 MII and HDLC nibble
Input
I2C: SCL
Input/ Output
1-30
Communications Processor Module (CPM) Ports
1.7.3 Port C Signals
Table 1-9. Port C Signals
Name GeneralPurpose I/O
PC31
Peripheral Controller: Dedicated I/O Protocol
BRG1O
Dedicated I/O Data Direction
Output
Description
Baud-Rate Generator 1 Output The CPM supports up to 8 BRGs. The BRGs can be used internally by the bank-of-clocks selection logic and/or provide an output to one of the 8 BRG pins. BRG1O can be the internal input to the SIU timers. When CLK5 is selected (see PC27 below), it is the source for BRG1O which is the default input for the SIU timers. See the System Interface Unit (SIU) chapter in the MSC8103 Technical Reference manual for additional information. If CLK5 is not enabled, BRG1O uses an internal input. If TMCLK is enabled (see PC26 below), the BRG1O input to the SIU timers is disabled. Clock 1 The CPM supports up to 10 clock input pins. The clocks are sent to the bank-of-clocks selection logic, where they can be routed to the controllers. Timer 1/2: Timer Gate 1 The timers can be gated/restarted by an external gate signal. There are two gate signals: TGATE1 controls timer 1 and/or 2 and TGATE2 controls timer 3 and/or 4. Baud-Rate Generator 2 Output The CPM supports up to 8 BRGs. The BRGs can be used internally by the bank-of-clocks selection logic and/or provide an output to one of the 8 BRG pins. Clock 2 The CPM supports up to 10 clock input pins. The clocks are sent to the bank-of-clocks selection logic, where they can be routed to the controllers. Timer 1: Timer Out 1 The timers (Timer[1-4]) can output a signal on a timer output (TOUT[1-4]) when the reference value is reached. This signal can be an active-low pulse or a toggle of the current output. The output can also connect internally to the input of another timer, resulting in a 32-bit timer. External Request 1 External request input line 1 asserts an internal request to the CPM processor. The signal can be programmed as level- or edge-sensitive, and also has programmable priority. Refer to the RISC Controller Configuration Register (RCCR) description in the Chapter 17 of the MSC8103 Reference Manual for programming information. There are no current microcode applications for this request line. It is reserved for future development.
CLK1
Input
TIMER1/2: TGATE1
Input
PC30
BRG2O
Output
CLK2
Input
Timer1: TOUT1
Output
EXT1
Input
1-31
Communications Processor Module (CPM) Ports
Table 1-9. Port C Signals (Continued)
Name GeneralPurpose I/O
PC29
Peripheral Controller: Dedicated I/O Protocol
BRG3O
Dedicated I/O Data Direction
Output
Description
Baud-Rate Generator 3 Output The CPM supports up to 8 BRGs. The BRGs can be used internally by the bank-of-clocks selection logic and/or provide an output to one of the 8 BRG pins. Clock 3 The CPM supports up to 10 clock input pins. The clocks are sent to the bank-of-clocks selection logic, where they can be routed to the controllers. Timer Input 2 A timer can have one of the following sources: another timer, system clock, system clock divided by 16 or a timer input. The CPM supports up to 4 timer inputs. The timer inputs can be captured on the rising, falling or both edges. SCC1: Clear to Send, Collision Typically used in conjunction with RTS. The MSC8103 SCC1 transmitter sends out a request to send data signal (RTS). The request is accepted when CTS is returned low. CLSN is the signal used in Ethernet mode. See also PC15. Baud-Rate Generator 4 Output The CPM supports up to 8 BRGs. The BRGs can be used internally by the bank-of-clocks selection logic and/or provide an output to one of the 8 BRG pins. Clock 4 The CPM supports up to 10 clock input pins. The clocks are sent to the bank-of-clocks selection logic, where they can be routed to the controllers. Timer Input 1 A timer can have one of the following sources: another timer, system clock, system clock divided by 16 or a timer input. The CPM supports up to 4 timer inputs. The timer inputs can be captured on the rising, falling or both edges. Timer 2: Timer Output 2 The timers (Timer[1-4]) can output a signal on a timer output (TOUT[1-4]) when the reference value is reached. This signal can be an active-low pulse or a toggle of the current output. The output can also be connected internally to the input of another timer, resulting in a 32-bit timer. SCC2: Clear to Send, Collision Typically used in conjunction with RTS. The MSC8103 SCC2 transmitter sends out a request to send data signal (RTS). The request is accepted when CTS is returned low. CLSN is the signal used in Ethernet mode. See also PC13.
CLK3
Input
TIN2
Input
SCC1: CTS, CLSN
Input
PC28
BRG4O
Output
CLK4
Input
TIN1
Input
Timer2: TOUT2
Output
SCC2: CTS, CLSN
Input
1-32
Communications Processor Module (CPM) Ports
Table 1-9. Port C Signals (Continued)
Name GeneralPurpose I/O
PC27
Peripheral Controller: Dedicated I/O Protocol
BRG5O
Dedicated I/O Data Direction
Output
Description
Baud-Rate Generator 5 Output The CPM supports up to 8 BRGs. The BRGs can be used internally by the bank-of-clocks selection logic and/or provide an output to one of the 8 BRG pins. Clock 5 When selected, CLK5 is a source for the SIU timers via BRG1O. See the System Interface Unit (SIU) chapter in the MSC8103 Technical Reference manual for additional information. If CLK5 is not enabled, BRG1O uses an internal input. If TMCLK is enabled (see PC26 below), the BRG1O input to the SIU timers is disabled. Timer 3/4: Timer Gate 2 The timers can be gated/restarted by an external gate signal. There are two gate signals: TGATE1 controls timer 1 and/or 2 and TGATE2 controls timer 3 and/or 4. Baud-Rate Generator 6 Output The CPM supports up to 8 BRGs. The BRGs can be used internally by the bank-of-clocks selection logic and/or provide an output to one of the 8 BRG pins. Clock 6 The CPM supports up to 10 clock input pins. The clocks are sent to the bank-of-clocks selection logic, where they can be routed to the controllers. Timer 3: Timer Out 3 The timers (Timer[1-4]) can output a signal on a timer output (TOUT[1-4]) when the reference value is reached. This signal can be an active-low pulse or a toggle of the current output. The output can also connect internally to the input of another timer, resulting in a 32-bit timer. Timer Clock When selected, TMCLK is the designated input to the SIU timers. When TMCLK is configured as the input to the SIU timers, the BRG1O input is disabled. See the System Interface Unit (SIU) chapter in the MSC8103 Technical Reference manual for additional information.
CLK5
Input
TIMER3/4: TGATE2
Input
PC26
BRG6O
Output
CLK6
Input
Timer3: TOUT3
Output
TMCLK
Input
1-33
Communications Processor Module (CPM) Ports
Table 1-9. Port C Signals (Continued)
Name GeneralPurpose I/O
PC25
Peripheral Controller: Dedicated I/O Protocol
BRG7O
Dedicated I/O Data Direction
Output
Description
Baud-Rate Generator 7 Output The CPM supports up to 8 BRGs. The BRGs can be used internally by the bank-of-clocks selection logic and/or provide an output to one of the 8 BRG pins. Clock 7 The CPM supports up to 10 clock input pins. The clocks are sent to the bank-of-clocks selection logic, where they can be routed to the controllers. Timer Input 4 A timer can have one of the following sources: another timer, system clock, system clock divided by 16 or a timer input. The CPM supports up to 4 timer inputs. The timer inputs can be captured on the rising, falling or both edges. DMA: Data Acknowledge 2 DACK2, DREQ2, DRACK2 and DONE2 belong to the SIU DMA. DONE2 and DRACK2 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pins associated with the PIO ports. Baud-Rate Generator 8 Output The CPM supports up to 8 BRGs. The BRGs can be used internally by the bank-of-clocks selection logic and/or provide an output to one of the 8 BRG pins. Clock 8 The CPM supports up to 10 clock input pins. The clocks are sent to the bank-of-clocks selection logic, where they can be routed to the controllers. Timer Input 3 A timer can have one of the following sources: another timer, system clock, system clock divided by 16, or a timer input. The CPM supports up to four timer inputs. The timer inputs can be captured on the rising, falling, or both edges. Timer 4: Timer Out 4 The timers (Timer1-4]) can output a signal on a timer output (TOUT[1-4]) when the reference value is reached. This signal can be an active-low pulse or a toggle of the current output. The output can also be connected internally to the input of another timer, resulting in a 32-bit timer. DMA: Data Request 2 DACK2, DREQ2, DRACK2, and DONE2 belong to the SIU DMA. DONE2 and DRACK2 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pins associated with the PIO ports.
CLK7
Input
TIN4
Input
DMA: DACK2
Output
PC24
BRG8O
Output
CLK8
Input
TIN3
Input
Timer4: TOUT4
Output
DMA: DREQ2
Input
1-34
Communications Processor Module (CPM) Ports
Table 1-9. Port C Signals (Continued)
Name GeneralPurpose I/O
PC23
Peripheral Controller: Dedicated I/O Protocol
CLK9
Dedicated I/O Data Direction
Input
Description
Clock 9 The CPM supports up to 10 clock input pins. The clocks are sent to the bank-of-clocks selection logic, where they can be routed to the controllers. DMA: Data Acknowledge 1 DACK1, DREQ1, DRACK1, and DONE1 belong to the SIU DMA. DONE1 and DRACK1 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pins associated with the PIO ports. External Request 2 External request input line 2 asserts an internal request to the CPM processor. The signal can be programmed as level- or edge-sensitive, and also has programmable priority. Refer to the RISC Controller Configuration Register (RCCR) description in the Chapter 17 of the MSC8103 Reference Manual for programming information. There are no current microcode applications for this request line. It is reserved for future development. Serial Interface 1: Layer 1 Strobe 1 In the time-slot assigner supported by SI1. The MSC8103 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture. These strobes can also generate output wave forms for such applications as stepper-motor control. Clock 10 The CPM supports up to 10 clock input pins. The clocks are sent to the bank-of-clocks selection logic, where they can be routed to the controllers. DMA: Request 1 DACK1, DREQ1, DRACK1, and DONE1 belong to the SIU DMA. DONE1 and DRACK1 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pins associated with the PIO ports.
DMA: DACK1
Output
EXT2
Input
PC22
SI1: L1ST1
Output
CLK10
Input
DMA: DREQ1
Input/ Output
1-35
Communications Processor Module (CPM) Ports
Table 1-9. Port C Signals (Continued)
Name GeneralPurpose I/O
PC15
Peripheral Controller: Dedicated I/O Protocol
SMC2: SMTXD
Dedicated I/O Data Direction
Output
Description
SMC2: Serial Management Transmit Data Supported by SMC2. The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock. Not all signals are used for all applications. SMCs are full-duplex ports that support three protocols or modes: UART, transparent, or general-circuit interface (GCI). See also PA9. SCC1: Clear To Send, Collision Typically used in conjunction with RTS. The MSC8103 SCC1 transmitter sends out a request to send data signal (RTS). The request is accepted when CTS is returned low. CLSN is the signal used in Ethernet mode. See also PC29. FCC1: UTOPIA Master Transmit Address Bit 0 In the ATM UTOPIA master interface supported by FCC1, this is transmit address bit 0. FCC1: UTOPIA Slave Transmit Address Bit 0 In the ATM UTOPIA slave interface supported by FCC1, this is transmit address bit 0. Serial Interface 1: Layer 1 Strobe 2 In the time-slot assigner supported by SI1. The MSC8103 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture. These strobes can also be generate output wave forms for such applications as stepper-motor control. SCC1: Carrier Detect, Receive Enable Typically used in conjunction with RTS supported by SCC1. The MSC8103 SCC1 transmitter requests the receiver to send data by asserting RTS low. The request is accepted when CTS is returned low. FCC1: UTOPIA Multi-PHY Master Receive Address Bit 0 In the ATM UTOPIA master interface supported by FCC1, this is receive address bit 0. FCC1: UTOPIA Multi-PHY Slave Receive Address Bit 0 In the ATM UTOPIA slave interface supported by FCC1, this is receive address bit 0.
SCC1: CTS/CLSN
Input
FCC1: TXADDR0 UTOPIA master
Output
FCC1: TXADDR0 UTOPIA slave PC14 SI1: L1ST2
Input
Output
SCC1: CD, RENA
Input
FCC1: RXADDR0 UTOPIA master
Output
FCC1: RXADDR0 UTOPIA slave
Input
1-36
Communications Processor Module (CPM) Ports
Table 1-9. Port C Signals (Continued)
Name GeneralPurpose I/O
PC13
Peripheral Controller: Dedicated I/O Protocol
SI1: L1ST4
Dedicated I/O Data Direction
Output
Description
Serial Interface 1: Layer 1 Strobe 4 In the time-slot assigner supported by SI1. The MSC8103 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture. These strobes can also generate output wave forms for such applications as stepper-motor control. SCC2: Clear to Send, Collision Typically used in conjunction with RTS. The MSC8103 SCC2 transmitter sends out a request to send data signal (RTS). The request is accepted when CTS is returned low. CLSN is the signal used in Ethernet mode. See also PC28. FCC1: UTOPIA Multi-PHY Master Transmit Address Bit 1 In the ATM UTOPIA master interface supported by FCC1, this is transmit address bit 1. FCC1: UTOPIA Multi-PHY Slave Transmit Address Bit 1 In the ATM UTOPIA slave interface supported by FCC1, this is transmit address bit 1. Serial Interface 1: Layer 1 Strobe 3 In the time-slot assigner supported by SI1. The MSC8103 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture. These strobes can also generate output wave forms for such applications as stepper-motor control. SCC2: Carrier Detect, Request Enable Typically used in conjunction with RTS supported by SCC2. The MSC8103 SCC2 transmitter requests to the receiver that it sends data by asserting RTS low. The request is accepted when CTS is returned low. FCC1: UTOPIA Multi-PHY Master Receive Address Bit 1 In the ATM UTOPIA master interface supported by FCC1, this is receive address bit 1. FCC1: UTOPIA Multi-PHY Slave Receive Address Bit 1 In the ATM UTOPIA slave interface supported by FCC1, this is receive address bit 1.
SCC2: CTS,CLSN
Input
FCC1:TXADDR1 UTOPIA master
Output
FCC1: TXADDR1 UTOPIA slave PC12 SI1: L1ST3
Input
Output
SCC2: CD, RENA
Input
FCC1: RXADDR1 UTOPIA master
Output
FCC1: RXADDR1 UTOPIA slave
Input
1-37
Communications Processor Module (CPM) Ports
Table 1-9. Port C Signals (Continued)
Name GeneralPurpose I/O
PC7
Peripheral Controller: Dedicated I/O Protocol
SI2: L1ST1
Dedicated I/O Data Direction
Output
Description
Serial Interface 2: Strobe 1 In the time-slot assigner supported by SI2. The MSC8103 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture. These strobes can also generate output wave forms for such applications as stepper-motor control. FCC1: Clear To Send In the standard modem interface signals supported by FCC1 (RTS, CTS, and CD). CTS is asynchronous with the data. FCC1: UTOPIA Multi-PHY Master Transmit Address Bit 2 In the ATM UTOPIA master interface supported by FCC1, this is transmit address bit 2. FCC1: UTOPIA Multi-PHY Slave Transmit Address Bit 2 In the ATM UTOPIA slave interface supported by FCC1 using multiplexed polling, this is transmit address bit 2. FCC1: UTOPIA Multi-PHY Master Transmit Cell Available 1 Direct Polling In the ATM UTOPIA master interface supported by FCC1 using direct polling, TXCLAV1 is asserted by an external UTOPIA slave PHY to indicate that it can accept one complete ATM cell.
FCC1: CTS HDLC serial, HDLC nibble, and transparent FCC1: TXADDR2 UTOPIA master
Input
Output
FCC1: TXADDR2 UTOPIA slave
Input
FCC1: TXCLAV1 UTOPIA multi-PHY master, direct polling
Input
1-38
Communications Processor Module (CPM) Ports
Table 1-9. Port C Signals (Continued)
Name GeneralPurpose I/O
PC6
Peripheral Controller: Dedicated I/O Protocol
SI2: L1ST2
Dedicated I/O Data Direction
Output
Description
Serial Interface 2: Layer 1 Strobe 2 In the time-slot assigner supported by SI2. The MSC8103 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture. These strobes can also generate output wave forms for such applications as stepper-motor control. FCC1: Carrier Detect In the standard modem interface signals supported by FCC1 (RTS, CTS, and CD). CD is an input asynchronous with the data. FCC1: UTOPIA Multi-PHY Master Receive Address Bit 2 In the ATM UTOPIA master interface supported by FCC1, this is receive address bit 2. FCC1: UTOPIA Slave Receive Address Bit 2 In the ATM UTOPIA slave interface supported by FCC1 using multiplexed polling, this is receive address bit 2. FCC1: UTOPIA Multi-PHY Master Receive Cell Available 1 Direct Polling In the ATM UTOPIA master interface supported by FCC1 using direct polling, RXCLAV1 is asserted by an external PHY when one complete ATM cell is available for transfer. SMC1: Transmit Data Supported by SMC1. The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock. Not all signals are used for all applications. SMCs are full-duplex ports that supports three protocols or modes: UART, transparent, or general-circuit interface (GCI). Serial Interface 2: Layer 1 Strobe 3 In the time-slot assigner supported by SI2. The MSC8103 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture. These strobes can also generate output wave forms for such applications as stepper-motor control. FCC2: Clear To Send In the standard modem interface signals supported by FCC2 (RTS, CTS, and CD). CTS is asynchronous with the data.
FCC1: CD HDLC serial, HDLC nibble, and transparent
Input
FCC1: RXADDR2 UTOPIA master
Output
FCC1: RXADDR2 UTOPIA slave
Input
FCC1: RXCLAV1 UTOPIA multi-PHY master, direct polling
Input
PC5
SMC1: SMTXD
Output
SI2: L1ST3
Output
FCC2: CTS HDLC serial, HDLC nibble, and transparent
Input
1-39
Communications Processor Module (CPM) Ports
Table 1-9. Port C Signals (Continued)
Name GeneralPurpose I/O
PC4
Peripheral Controller: Dedicated I/O Protocol
SMC1: SMRXD
Dedicated I/O Data Direction
Input
Description
SMC1: Receive Data Supported by SMC1. The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock. Not all signals are used for all applications. SMCs are full-duplex ports that supports three protocols or modes: UART, transparent, or general-circuit interface (GCI). Serial Interface 2: Layer 1 Strobe 4 In the time-slot assigner supported by SI2. The MSC8103 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture. These strobes can also generate output wave forms for such applications as stepper-motor control. FCC2: Carrier Detect In the standard modem interface signals supported by FCC2 (RTS, CTS and CD). CD is asynchronous with the data.
SI2: L1ST4
Output
FCC2: CD HDLC serial, HDLC nibble, and transparent
Input
1-40
Communications Processor Module (CPM) Ports
1.7.4 Port D Signals
Table 1-10. Port D Signals
Name GeneralPurpose I/O
PD31
Peripheral Controller: Dedicated I/O Protocol
SCC1: RXD
Dedicated I/O Data Direction
Input
Description
SCC1: Receive Data Supported by SCC1. SCC1 receives serial data from RXD. DMA: Data Request Acknowledge 1 DACK1, DREQ1, DRACK1, and DONE1 belong to the SIU DMA. DONE1 and DRACK1 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pins associated with the PIO ports. DMA: Done 1 DACK1, DREQ1, DRACK1, and DONE1 belong to the SIU DMA. DONE1 and DRACK1 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pins associated with the PIO ports. SCC1: Transmit Data Supported by SCC1. SCC1 transmits serial data out of TXD. DMA: Data Request Acknowledge 2 DACK2, DREQ2, DRACK2, and DONE2 belong to the SIU DMA. DONE2 and DRACK2 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pins associated with the PIO ports. DMA: Done 2 DACK2, DREQ2, DRACK2, and DONE2 belong to the SIU DMA. DONE2 and DRACK2 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pins associated with the PIO ports. SCC1: Request to Send, Transmit Enable Typically used in conjunction with CD supported by SCC2. The MSC8103 SCC1 transmitter requests the receiver to send data by asserting RTS low. The request is accepted when CTS is returned low. TENA is the signal used in Ethernet mode. FCC1: UTOPIA Multi-PHY Master Receive Address Bit 3 In the ATM UTOPIA master interface supported by FCC1 using multiplexed polling, this is receive address bit 3. FCC1: UTOPIA Slave Receive Address Bit 3 In the ATM UTOPIA slave interface supported by FCC1 using multiplexed polling, this is receive address bit 3. FCC1: UTOPIA Multi-PHY Master Receive Cell Available 2 Direct Polling In the ATM UTOPIA master interface supported by FCC1 using direct polling, RXCLAV2 is asserted by an external PHY when one complete ATM cell is available for transfer.
DMA: DRACK1
Output
DMA: DONE1
Input/ Output
PD30
SCC1: TXD
Output
DMA: DRACK2
Output
DMA: DONE2
Input/ Output
PD29
SCC1: RTS, TENA
Output
FCC1: RXADDR3 UTOPIA master
Output
FCC1: RXADDR3 UTOPIA slave
Input
FCC1: RXCLAV2 UTOPIA multi-PHY master, direct polling
Input
1-41
Communications Processor Module (CPM) Ports
Table 1-10. Port D Signals (Continued)
Name GeneralPurpose I/O
PD19
Peripheral Controller: Dedicated I/O Protocol
FCC1: TXADDR4 UTOPIA master
Dedicated I/O Data Direction
Output
Description
FCC1: Multi-PHY Master Transmit Address Bit 4 Multiplexed Polling In the ATM UTOPIA master interface supported by FCC1 using multiplexed polling, this is transmit address bit 4. FCC1: UTOPIA Slave Transmit Address Bit 4 In the ATM UTOPIA slave interface supported by FCC1 using multiplexed polling, this is transmit address bit 4. FCC1: UTOPIA Multi-PHY master Transmit Cell Available 3 Direct Polling In the ATM UTOPIA master interface supported by FCC1 using direct polling, TXCLAV3 is asserted by an external UTOPIA slave PHY to indicate that it can accept one complete ATM cell. Baud Rate Generator 1 Output The CPM supports up to 8 BRGs. The BRGs can be used internally by the bank-of-clocks selection logic and/or provide an output to one of the 8 BRG pins. BRG1O can be the internal input to the SIU timers. When CLK5 is selected (see PC27 above), it is the source for BRG1O which is the default input for the SIU timers. See the System Interface Unit (SIU) chapter in the MSC8103 Technical Reference manual for additional information. If CLK5 is not enabled, BRG1O uses an internal input. If TMCLK is enabled (see PC26 above), the BRG1O input to the SIU timers is disabled. SPI: Select The SPI interface comprises four signals: master out slave in (SPIMOSI), master in slave out (SPIMISO), clock (SPICLK) and select (SPISEL). The SPI can be configured as a slave or master in single- or multiple-master environments. SPISEL is the enable input to the SPI slave. In a multimaster environment, SPISEL (always an input) detects an error when more than one master is operating. SPI masters must output a slave select signal to enable SPI slave devices by using a separate general-purpose I/O signal. Assertion of an SPI SPISEL while it is master causes an error.
FCC1: TXADDR4 UTOPIA slave
Input
FCC1: TXCLAV3 UTOPIA multi-PHY master, direct polling
Input
BRG1O
Output
SPI: SPISEL
Input
1-42
Communications Processor Module (CPM) Ports
Table 1-10. Port D Signals (Continued)
Name GeneralPurpose I/O
PD18
Peripheral Controller: Dedicated I/O Protocol
FCC1: RXADDR4 UTOPIA master
Dedicated I/O Data Direction
Output
Description
FCC1: UTOPIA Master Receive Address Bit 4 In the ATM UTOPIA master interface supported by FCC1 using multiplexed polling, this is receive address bit 4. FCC1: UTOPIA Slave Receive Address Bit 4 In the ATM UTOPIA slave interface supported by FCC1, this is the receive address bit 4. FCC1: UTOPIA Multi-PHY Master Receive Cell Available 3 Direct Polling In the ATM UTOPIA master interface supported by FCC1 using direct polling, RXCLAV3 is asserted by an external PHY when one complete ATM cell is available for transfer. SPI: Clock The SPI interface comprises four signals: master out slave in (SPIMOSI), master in slave out (SPIMISO), clock (SPICLK) and select (SPISEL). The SPI can be configured as a slave or master in single- or multiple-master environments. SPICLK is a gated clock, active only during data transfers. Four combinations of SPICLK phase and polarity can be configured. When the SPI is a master, SPICLK is the clock output signal that shifts received data in from SPIMISO and transmitted data out to SPIMOSI. Baud Rate Generator 2 Output The CPM supports up to 8 BRGs. The BRGs can be used internally to the MSC8103 and/or provide an output to one of the 8 BRG pins. FCC1: UTOPIA Receive Parity In the ATM UTOPIA interface supported by FCC1, this is the odd parity bit for RXD[0-7]. SPI: Master Output Slave Input The SPI interface comprises our signals: master out slave in (SPIMOSI), master in slave out (SPIMISO), clock (SPICLK) and select (SPISEL). The SPI can be configured as a slave or master in single- or multiple-master environments. When the SPI is a slave, SPICLK is the clock input that shifts received data in from SPIMOSI and transmitted data out through SPIMISO. FCC1: UTOPIA Transmit Parity In the ATM UTOPIA interface supported by FCC1, this is the odd parity bit for TXD[0-7]. SPI: Master Input Slave Output The SPI interface comprises four signals: master out slave in (SPIMOSI), master in slave out (SPIMISO), clock (SPICLK), and select (SPISEL). The SPI can be configured as a slave or master in single- or multiple-master environments. When the SPI is a slave, SPICLK is the clock input that shifts received data in from SPIMOSI and transmitted data out through SPIMISO.
FCC1: RXADDR4 UTOPIA slave
Input
FCC1: RXCLAV3 UTOPIA multi-PHY master, direct polling
Input
SPI: SPICLK
Input/ Output
PD17
BRG2O
Output
FCC1: RXPRTY UTOPIA
Input
SPI: SPIMOSI
Input/ Output
PD16
FCC1: TXPRTY UTOPIA
Output
SPI: SPIMISO
Input/ Output
1-43
JTAG Test Access Port Signals
Table 1-10. Port D Signals (Continued)
Name GeneralPurpose I/O
PD7
Peripheral Controller: Dedicated I/O Protocol
SMC1: SMSYN
Dedicated I/O Data Direction
Input
Description
SMC1: Serial Management Synchronization Supported by SMC1. SMSYN is an input. The SMC interface consists of SMTXD, SMRXD, SMSYN and a clock. Not all signals are used for all applications. SMCs are full-duplex ports that supports three protocols or modes: UART, transparent or general-circuit interface (GCI). FCC1: UTOPIA Master Transmit Address Bit 3 In the ATM UTOPIA master interface supported by FCC1 using multiplexed polling, this is transmit address bit 3. FCC1: UTOPIA Slave Transmit Cell Available 2 In the ATM UTOPIA slave interface supported by FCC1 using multiplexed polling, this is transmit address bit 3. FCC1: UTOPIA Multi-PHY Master Transmit Cell Available 2 Direct Polling In the ATM UTOPIA master interface supported by FCC1 using direct polling, TXCLAV2 is asserted by an external UTOPIA slave PHY to indicate that it can accept one complete ATM cell.
FCC1: TXADDR3 UTOPIA master
Output
FCC1: TXADDR3 UTOPIA slave
Input
FCC1: TXCLAV2 UTOPIA multi-PHY master, direct polling
Input
1.8 JTAG Test Access Port Signals
The MSC8103 supports the standard set of Test Access Port (TAP) signals defined by IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture specification and described in Table 1-11. Table 1-11. JTAG Test Access Port Signals
Signal Name
TCK TDI
Type
Input Input
Signal Description
Test Clock--A test clock signal for synchronizing JTAG test logic. Test Data Input--A test data serial signal for test instructions and data. TDI is sampled on the rising edge of TCK and has an internal pull-up resistor. Test Data Output--A test data serial signal for test instructions and data. TDO can be tri-stated. The signal is actively driven in the shift-IR and shift-DR controller states and changes on the falling edge of TCK. Test Mode Select--Sequences the test controller's state machine, is sampled on the rising edge of TCK, and has an internal pull-up resistor. Test Reset--Asynchronously initializes the test controller, has an internal pull-up resistor, and must be asserted after power up.
TDO
Output
TMS
Input
TRST
Input
1-44
Reserved Signals
1.9 Reserved Signals
Table 1-12. Reserved Signals
Signal Name
TEST
Type
Input
Signal Description
Test Used for manufacturing testing. You must connect this input to GND. Leave disconnected. Spare Pins Leave disconnected for backward compatibility with future revisions of this device.
THERM[1-2] SPARE1, 5
-- --
1-45
Reserved Signals
1-46
Chapter 2
Specifications
2.1 Introduction
This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MSC8103 communications processor. For additional information, see the MSC8103 Reference Manual.
2.2 Absolute Maximum Ratings
CAUTION
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or VCC). In calculating timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a "maximum" value for a specification never occurs in the same device with a "minimum" value for another specification; adding a maximum to a minimum represents a condition that can never exist.
2-1
Recommended Operating Conditions
Table 2-1 describes the maximum electrical ratings for the MSC8103. Table 2-1. Absolute Maximum Ratings2
Rating
Core supply voltage3 PLL supply voltage3 I/O supply Input voltage3
Symbol
VDD VCCSYN V DDH VIN
Value
-0.2 to 1.7 -0.2 to 1.7 -0.2 to 3.6 (GND - 0.2) to 3.6 -40 to 120 -55 to +150
Unit
V V V V C C
voltage3 range4
Maximum operating temperature Storage temperature range Notes: 1. 2. 3.
TJ TSTG
4.
Functional operating conditions are given in Table 2-2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the listed limits may affect device reliability or cause permanent damage. The input voltage must not exceed the I/O supply VDDH by more than 2.5 V at any time, including during power-on reset. In turn, VDDH can exceed V DD/V CCSYN by more than 3.3 V during power-on reset, but for no more than 100 ms. VDDH should not exceed VDD/V CCSYN by more than 2.1 V during normal operation. VDD/V CCSYN must not exceed VDDH by more than 0.4 V at any time, including during power-on reset. See Section 4.2, Electrical Design Considerations, on page 4-2 for more information. Section 4.1, Thermal Design Considerations, on page 4-1 includes a formula for computing the chip junction temperature (TJ ).
2.3 Recommended Operating Conditions
Table 2-2 lists recommended operating conditions. Proper device operation outside of these conditions is not guaranteed. Table 2-2. Recommended Operating Conditions
Rating
SC140 Core supply voltage PLL supply voltage I/O supply voltage Input voltage Operating temperature range
Symbol
VDD VCCSYN VDDH VIN TJ
Value
275 MHz: 1.5 to 1.7 300 MHz: 1.55 to 1.7 275 MHz: 1.5 to 1.7 300 MHz: 1.55 to 1.7 3.135 to 3.465 -0.2 to VDDH + 0.2 275 MHz: -40 to 105 300 MHz: -40 to 75
Unit
V V V V V V C C
2-2
Thermal Characteristics
2.4 Thermal Characteristics
Table 2-3 describes thermal characteristics of the MSC8103. Table 2-3. Thermal Characteristics
Characteristic
Junction-to-ambient1, 2 Junction-to-board (bottom) Junction-to-case (top)4 Notes: 1.
3
Symbol
RJA or JA RJB or JB RJC or JC
Lidded FC-PBGA 17 x 17mm
26 9.5 0.8
Unit
C/W C/W C/W
2. 3. 4.
5.
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per SEMI G38-87 and EIA/JESD51-2 with the single layer (1s) board horizontal. Thermal resistance between the die and the printed circuit board per JESD 51-8. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for case temperature. Numbers based on simulations. Actual values TBD.
See Section 4.1, Thermal Design Considerations, on page 4-1 for details on these characteristics.
2.5 DC Electrical Characteristics
This section describes the DC electrical characteristics for the MSC8103. The measurements in Table 2-4 assume the following system conditions: * * * * TJ = 0 - 100 C VDD = 1.6 V 5% VDC VDDH = 3.3 V 5% VDC GND = 0 VDC The leakage current is measured for nominal VDDH and VDD or both VDDH and VDD must vary in the same direction (for example, both VDDH and VDD vary by 5 percent). Table 2-4. DC Electrical Characteristics
Characteristic
Input high voltage, all inputs except CLKIN Input low voltage CLKIN input high voltage CLKIN input low voltage1 Input leakage current, VIN = VDDH Tri-state (high impedance off state) leakage current, VIN = VDDH Signal low input current, VIL = 0.4 V Signal high input current, VIH = 2.0 V Output high voltage, IOH = -2 mA, except open drain pins Output low voltage, IOL= 3.2 mA Notes: 1.
Note:
Symbol
VIH VIL V IHC VILC IIN IOZ IL IH VOH V OL
Min
2.0 GND 2.5 GND -- -- -- -- 2.4 --
Max
3.465 0.8 3.465 0.8 10 10 -4.0 4.0 -- 0.4
Unit
V V V V A A mA mA V V
The optimum CLKIN duty cycle is obtained when: VILC = VDDH - VIHC .
2-3
Clock Configuration
Table 2-5. Typical Power Dissipation
Characteristic
Core power dissipation at 300 MHz CPM power dissipation at 200 MHz SIU power dissipation at 100 MHz Core leakage power CPM leakage power SIU leakage power
Symbol
PCORE PCPM PSIU PLCO P LCP PLSI
Typical
450 320 80 3 6 2
Unit
mW mW mW mW mW mW
2.6 Clock Configuration
The following sections provide a general description of clock configuration.
2.6.1 Valid Clock Modes
Table 2-6 shows the maximum frequency values for each rated core frequency (275 or 300 MHz). The user must ensure that maximum frequency values are not exceeded. Table 2-6. Maximum Frequencies
Characteristic
Core Frequency CPM Frequency (CPMCLK) Bus Frequency (BCLK) Serial Communication Controller Clock Frequency (SCLK) Baud Rate Generator Clock Frequency (BRGCLK) External Clock Output Frequency (CLKOUT)
Maximum Frequency in MHz
275 183.33 91.67 91.67 91.67 91.67 300 200 100 100 100 100
Six bit values map the MSC8103 clocks to one of the valid configuration mode options. Each option determines the CLKIN, SC140 core, system bus, SCC clock, CPM, and CLKOUT frequencies. The six bit values are derived from three dedicated input pins (MODCK[1-3]) and three bits from the hard reset configuration word (MODCK_H). To configure the SPLL pre-division factor, SPLL multiplication factor, and the frequencies for the SC140 core, SCC clocks, CPM parallel I/O ports, and system buses, the MODCK[1-3] pins are sampled and combined with the MODCK_H values when the internal power-on reset (internal PORESET) is deasserted. Clock configuration changes only when the internal PORESET signal is deasserted. The following factors are configured: * * * * * * * SPLL pre-division factor (SPLL PDF) SPLL multiplication factor (SPLL MF) Bus post-division factor (Bus DF) CPM division factor (CPM DF) Core division factor (Core DF) CPLL pre-division factor (CPLL PDF) CPLL multiplication factor (CPLL MF)
The SCC division factor (SCC DF) is fixed at 4. The BRG division factor (BRG DF) is configured through the System Clock Control Register (SCCR) and can be 4, 16 (default after reset), 64, or 256. Note: Refer to AN2306/D Clock Mode Selection for MSC8101 and MSC8103 Mask Set 2K87M for details on clock configuration.
2-4
Clock Configuration
2.6.2 Clocks Programming Model
This section describes the clock registers in detail. The registers discussed are as follows: * System Clock Control Register (SCCR) * System Clock Mode Register (SCMR)
2.6.2.1 System Clock Control Register
Bit
TYPE RESET
0
1
2
3
4
5
6
7
8 --
Reserved --
9
10
11
12
13
14
15
Bit
TYPE RESET
16
17
18
19
20
21
-- Reserved --
22
23
24
25
26
27
CLKODIS
28 --
29
30
31
DFBRG R/W
R/W
Reserved
0
--
0
1
Figure 2-1. System Clock Control Register (SCCR)--0x10C80 The SCCR is memory-mapped into the SIU register map of the MSC8103. Table 2-7. SCCR Bit Descriptions
Defaults Name Bit No.
-- 0-26 CLKODIS 27
PORESET
-- 0
Hard Reset
--
Description
Reserved. Write to 0 fro future compatibility.
Settings
Unaffected CLKOUT Disable 0 Disables the CLKOUT signal. The value of 1 CLKOUT when disabled is indeterminate (can be 1 or 0). -- Reserved. Write to 0 fro future compatibility. 00 01 10 11
CLKOUT enabled (default) CLKOUT disabled
-- 28-29 DFBRG 30-31
-- 01
Unaffected Division Factor for the BRG Clock Defines the BRGCLK frequency. Changing this value does not result in a loss of lock condition.
Divide by 4 Divide by 16 (default value) Divide by 64 Divide by 256
2-5
Clock Configuration
2.6.2.2 System Clock Mode Register
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
COREPDF TYPE RESET
COREMF R --
BUSDF
CPMDF
16
17
18
19
20
21
22
23
24
-- R --
25
DLLDIS
26
--
27
28
29
30
31
SPLLPDF TYPE RESET
SPLLMF
COREDF
Figure 2-2. System Clock Mode Register (SCMR)--0x10C88 SCMR is a read-only register that is updated during power-on reset (PORESET) and provides the mode control signals to the PLLs, DLL, and clock logic. This register reflects the currently defined configuration settings. For details of the available setting options, see AN2306/D. Table 2-8. SCMR Field Descriptions
Defaults Name Bit No. PORESET Hard Reset Description Settings
COREPDF Configuration Unaffected Core PLL Pre-Division Factor 0-3 Pins
0000 0001 0010 0011 All other 0101 0110 0111 All other 0001 0010 0011 0100 0101 All other 0000 0001 0010 All other 0000 0001 0010 0011 0100 0101 All other
CPLL PDF = 1 CPLL PDF = 2 CPLL PDF = 3 CPLL PDF = 4 combinations not used. CPLL MF = 10 CPLL MF = 12 CPLL MF = 14 combinations not used. Bus DF = 2 Bus DF = 3 Bus DF = 4 Bus DF = 5 Bus DF = 6 combinations not used. CPM DF = 1 CPM DF = 2 CPM DF = 3 combinations not used. SPLL PDF = 1 SPLL PDF = 2 SPLL PDF = 3 SPLL PDF = 4 SPLL PDF = 5 SPLL PDF = 6 combinations not used
COREMF 4-7
Configuration Unaffected Core Multiplication Factor Pins
BUSDF 8-11
Configuration Unaffected 60x-compatible Bus Division Factor Pins
CPMDF 12-15
Configuration Unaffected CPM Division Factor Pins
SPLLPDF 16-19
Configuration Unaffected SPLL Pre-Division Factor Pins
2-6
AC Timings
Table 2-8. SCMR Field Descriptions (Continued)
Defaults Name Bit No.
SPLLMF 20-23
PORESET
Hard Reset
Description
Settings
Configuration Unaffected SPLL Multiplication Factor Pins
0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 All other
SPLL MF = 10 SPLL MF = 12 SPLL MF = 14 SPLL MF = 16 SPLL MF = 18 SPLL MF = 20 SPLL MF = 22 SPLL MF = 24 SPLL MF = 26 SPLL MF = 28 SPLL MF = 30 combinations not used
-- 24 DLLDIS 25 -- 26-27 COREDF 28-31
--
--
Reserved 0 1 DLL operation is enabled DLL is disabled
Configuration Unaffected DLL Disable Pins -- -- Reserved
Configuration Unaffected Core Division Factor Pins
0000 0001 0010 0011 0100 0101 All other
CORE DF = 1 CORE DF = 2 CORE DF = 3 CORE DF = 4 CORE DF = 5 CORE DF = 6 combinations not used.
2.7 AC Timings
The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs. AC timings are based on a 50 pF load, except where noted otherwise, and 50 transmission line.
2.7.1 Output Buffer Impedances
Table 2-9. Output Buffer Impedances
Output Buffers
System Bus Memory Controller Parallel I/O Note:
Typical Impedance ()
35 35 55
These are typical values at 65C. The impedance may vary by 25% depending on device process and operating temperature.
2-7
AC Timings
2.7.2 Clocking and Timing Characteristics
Table 2-10. System Clock Parameters
Characteristic
Phase Jitter between BCLK and DLLIN CLKIN frequency1,2 CLKIN slope DLLIN slope CLKOUT frequency jitter Delay between CLKOUT and DLLIN Notes: 1. 2.
Minimum
-- 18 -- -- -- --
Maximum
0.5 75 5 2 (0.01 x CLKOUT) + CLKIN jitter 5
Unit
ns MHz ns ns ns ns
Low CLKIN frequency causes poor PLL performance. Choose a CLKIN frequency high enough to keep the frequency after the predivider (SPLLMFCLK) higher than 18 MHz. CLKIN should have a 50% 5% duty cycle.
Table 2-11. Clock Ranges
Maximum Rated Core Frequency Clock Symbol All Min
Input Clock SPLL MF Clock Bus/Output Serial Communications Controller Communications Processor Module SC140 Core Baud Rate Generator * For BRG DF = 4 * For BRG DF = 16 (default) * For BRG DF = 64 * For BRG DF = 256 CLKIN SPLLMFCLK BCLK CLKOUT SCLK CPMCLK DSPCLK BRGCLK 36 MHz 9 MHz 2.25 MHz 562.5 KHz 91.67 MHz 22.91 MHz 5.73 MHz 1.43 MHz 100 MHz 25 MHz 6.25 MHz 1.56 MHz 18 MHz 18 MHz 18 MHz 35 MHz 70 MHz 72 MHz
Max. Values for SC140 Clock Rating of: 275 MHz
91.67 MHz 34.38 MHz 91.67 MHz 91.67 MHz 183.3 MHz 275 MHz
300 MHz
100 MHz 37.5 MHz 100 MHz 100 MHz 200 MHz 300 MHz
2-8
AC Timings
2.7.3 Reset Timing
The MSC8103 has several inputs to the reset logic: * Power-on reset (PORESET) * External hard reset (HRESET) * External soft reset (SRESET) Asserting an external PORESET causes concurrent assertion of an internal PORESET signal, HRESET, and SRESET. When the external PORESET signal is deasserted, the MSC8103 samples several configuration pins: * * * *
RSTCONF--determines whether the MSC8103 is a master (0) or slave (1) device DBREQ--determines whether to operate in normal mode (0) or invoke the SC140 debug mode (1) HPE--disable (0) or enable (1) the host port (HDI16) BTM[0-1]--boot from external memory (00) or the HDI16 (01)
All these reset sources are fed into the reset controller, which takes different actions depending on the source of the reset. The reset status register indicates the last sources to cause a reset. Table 2-12 describes reset causes. Table 2-12. Reset Causes
Name
Power-on reset (PORESET) Hard reset (HRESET) Soft reset (SRESET)
Direction
Input Input/Output
Description
PORESET initiates the power-on reset flow that resets all the MSC8103s and configures various attributes of the MSC8103, including its clock mode. The MSC8103 can detect an external assertion of HRESET only if it occurs while the MSC8103 is not asserting reset. During HRESET, SRESET is asserted. HRESET is an open-drain pin. The MSC8103 can detect an external assertion of SRESET only if it occurs while the MSC8103 is not asserting reset. SRESET is an open-drain pin.
Input/Output
2.7.3.1 Reset Operation
The reset control logic determines the cause of a reset, synchronizes it if necessary, and resets the appropriate logic modules. The memory controller, system protection logic, interrupt controller, and parallel I/O pins are initialized only on hard reset. Soft reset initializes the internal logic while maintaining the system configuration. The MSC8103 has three mechanisms for reset configuration: host reset configuration, hardware reset configuration, and reduced reset configuration.
2.7.3.2 Power-On Reset Flow
Asserting the PORESET external pin initiates the power-on reset flow. PORESET should be asserted externally for at least 16 input clock cycles after external power to the MSC8103 reaches at least 2/3 VCC. As Table 2-13 shows, the MSC8103 has five configuration pins, four of which are multiplexed with the SC140 core EONCE Event (EE[0-1], EE[4-5]) pins and the fifth of which is the RSTCONF pin. These pins are sampled at the rising edge of PORESET. In addition to these configuration pins, three (MODCK[1-3]) pins are sampled by the MSC8103. The signals on these pins and the MODCK_H value in the Hard Reset Configuration Word determine the PLL locking mode, by defining the ratio between the DSP clock, the bus clocks, and the CPM clock frequencies.
2-9
AC Timings
Table 2-13. External Configuration Signals
Pin
RSTCONF
Description
Reset Configuration Input line sampled by the MSC8103 at the rising edge of PORESET. EONCE Event Bit 0 Input line sampled after SC140 core PLL locks. Holding EE0 high when PORESET is deasserted puts the SC140 core into Debug mode. 0 1 0 1
Settings
Reset Configuration Master. Reset Configuration Slave. SC140 core starts the normal processing mode after reset. SC140 core enters Debug mode immediately after reset. Host port disabled (hardware reset configuration enabled). Host port enabled.
DBREQ/ EE0
HPE/EE1
Host Port Enable 0 Input line sampled at the rising edge of PORESET. If asserted, the Host port is enabled, the system 1 data bus is 32-bit wide, and the Host must program the reset configuration word. Boot Mode Input lines sampled at the rising edge of PORESET, which determine the MSC8103 Boot mode. 00 01 10 11
BTM[0-1]/ EE[4-5]
MSC8103 boots from external memory. MSC8103 boots from HDI16. Reserved. Reserved.
Table 2-14. Reset Timing
No.
1
Characteristics
Required external PORESET duration minimum * CLKIN = 18 MHz * CLKIN = 75 MHz Delay from deassertion of external PORESET to deassertion of internal PORESET * CLKIN = 18 MHz * CLKIN = 75 MHz Delay from deassertion of internal PORESET to SPLL lock * SPLLMFCLK = 18 MHz * SPLLMFCLK = 25 MHz Delay from SPLL lock to DLL lock * DLL enabled -- BCLK = 18 MHz -- BCLK = 75 MHz * DLL disabled Delay from SPLL lock to HRESET deassertion * DLL enabled -- BCLK = 18 MHz -- BCLK = 75 MHz * DLL disabled -- BCLK = 18 MHz -- BCLK = 75 MHz Delay from SPLL lock to SRESET deassertion * DLL enabled -- BCLK = 18 MHz -- BCLK = 75 MHz * DLL disabled -- BCLK = 18 MHz -- BCLK = 75 MHz
Expression
16 / CLKIN
Min
Max
Unit
888.8 213.3 1024 / CLKIN 56.89 13.65 800 / SPLLMFCLK 44.4 32.0
-- --
ns ns
2
s s s s
3
4
3073 / BLCK 170.72 40.97 0.0
--
s s ns
5
3585 / BLCK 199.17 47.5 512 / BLCK 28.4 6.83
s s s s
6
3588 / BLCK 199.33 47.84 515 / BLCK 28.61 6.87
s s s s
Note:
Value given for lowest possible CLKIN frequency 18 MHz to ensure proper initialization of reset sequence.
2-10
AC Timings
2.7.3.3 Host Reset Configuration
Host reset configuration allows the host to program the reset configuration word via the Host port after PORESET is deasserted, as described in the MSC8103 Reference Manual. The MSC8103 samples the signals described in Table 2-13 one the rising edge of PORESET when the signal is deasserted. If HPE is sampled high, the host port is enabled. In this mode the RSTCONF pin must be pulled up. The device extends the internal PORESET until the host programs the reset configuration word register. The host must write four 8-bit half-words to the Host Reset Configuration Register address to program the reset configuration word, which is 32 bits wide. For more information, see the MSC8103 Reference Manual. The reset configuration word is programmed before the internal PLL and DLL in the MSC8103 are locked. The host must program it after the rising edge of the PORESET input. In this mode, the host must have its own clock that does not depend on the MSC8103 clock. After the PLL and DLL are locked, HRESET remains asserted for another 512 bus clocks and is then released. The SRESET is released three bus clocks later (see Figure 2-3).
1 PORESET Input PORESET Internal RSTCONF, HPE HRM, BTM pins are sampled
asserted for min 16 CLKIN.
Any time HRESET Output (I/O) Host programs Reset Configuration Word
MODCK[1-3] pins are sampled. MODCK_H bits are ready for PLL. PLL locked DLL locked
SRESET Output (I/O) 2 3 4 5 6
PLL locks after 800 SPLLMFCLKs and DLL locks 3073 BUS clocks after PLL is locked. When DLL is disabled, reset period is shortened by DLL lock time.
HRESET/SRESET are extended for 512/515 BUS clocks, respectively, from PLL and DLL lock
Figure 2-3. Host Reset Configuration Timing
2.7.3.4 Hardware Reset Configuration
Hardware reset configuration is enabled if HPE is sampled low at the rising edge of PORESET. The value driven on RSTCONF while PORESET changes from assertion to deassertion determines the MSC8103 configuration. If RSTCONF is deasserted (driven high) while PORESET changes, the MSC8103 acts as a configuration slave. If RSTCONF is asserted (driven low) while PORESET changes, the MSC8103 acts as a configuration master. Section 2.7.3.4, Hardware Reset Configuration, explains the configuration sequence and the terms "configuration master" and "configuration slave." Directly after the deassertion of PORESET and choice of the reset operation mode as configuration master or configuration slave, the MSC8103 starts the configuration process. The MSC8103 asserts HRESET and SRESET throughout the power-on reset process, including configuration. Configuration takes 1024 CLOCKIN cycles, after which MODCK[1-3] are sampled to determine the MSC8103 working mode.
2-11
AC Timings
Next, the MSC8103 halts until the SPLL locks. The SPLL locks according to MODCK[1-3], which are sampled, and to MODCK_H taken from the Reset Configuration Word. SPLL locking time is 800 reference clocks, which is the clock at the output of the SPLL Pre-divider. After the SPLL is locked, all the clocks to the MSC8103 are enabled. If the DLLDIS bit in the reset configuration word is reset, the DLL starts the locking process after the SPLL is locked. During PLL and DLL locking, HRESET and SRESET are asserted. HRESET remains asserted for another 512 BUS clocks and is then released. The SRESET is released three bus clocks later. If the DLLDIS bit in the reset configuration word is set, the DLL is bypassed and there is no locking process, thus saving the DLL locking time. Figure 2-4 shows the power-on reset flow.
1 PORESET Input PORESET Internal
asserted for min 16 CLKIN.
RSTCONF is sampled for master/slave determination
MODCK[1-3] are sampled. MODCK_H bits are ready for PLL. HRESET Output (I/O) PLL locked SRESET Output (I/O) 2 In reset configuration mode: reset configuration sequence occurs in this period. 3 DLL locked
4
5 6 HRESET/SRESET are extended for 512/515 bus clocks, respectively, from PLL and DLL Lock time.
PLL locks after 800 SPLLMFCLKs. DLL locks 3073 bus clocks after PLL is locked. When DLL is disabled, reset period is shortened by 3073 bus clocks.
Figure 2-4. Hardware Reset Configuration Timing
2-12
AC Timings
2.7.4 System Bus Access Timing
2.7.4.1 Core Data Transfers
Generally, all MSC8103 bus and system output signals are driven from the rising edge of the reference clock (REFCLK), which is DLLIN or, if the DLL is disabled, CLKOUT. Memory controller signals, however, trigger on four points within a REFCLK cycle. Each cycle is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge of REFCLK (and T3 at the falling edge), but the spacing of T2 and T4 depends on the PLL clock ratio selected, as Table 2-15 shows. Table 2-15. Tick Spacing for Memory Controller Signals
Tick Spacing (T1 Occurs at the Rising Edge of REFCLK) PLL Clock Ratio T2
1:2, 1:3, 1:4, 1:5, 1:6 1:2.5 1:3.5 1/4 REFCLK 3/10 REFCLK 4/14 REFCLK
T3
1/2 REFCLK 1/2 REFCLK 1/2 REFCLK
T4
3/4 REFCLK 8/10 REFCLK 11/14 REFCLK
Figure 2-5 is a graphical representation of Table 2-15.
REFCLK T1 REFCLK T1 REFCLK T1 T2 T3 T4 T2 T3 T4 T2 T3 T4
for 1:2, 1:3, 1:4, 1:5, 1:6
for 1:2.5
for 1:3.5
Figure 2-5. Internal Tick Spacing for Memory Controller Signals Note: The UPM machine and GPCM machine outputs change on the internal tick determined by the memory controller programming; the AC specifications are relative to the internal tick. SDRAM machine outputs change only on the REFCLK rising edge.
2-13
AC Timings
Table 2-16. AC Timing for SIU Inputs
No.
10 11a 11b 11c 11d
Characteristic
Hold time for all signals after the 50% level of the REFCLK rising edge ABB/AACK setup time before the 50% level of the REFCLK rising edge DBG/DBB/BR/TC setup time before the 50% level of the REFCLK rising edge ARTRY setup time before the 50% level of the REFCLK rising edge TA setup time before the 50% level of the REFCLK rising edge * Pipeline mode * Non-pipeline mode TEA setup time before the 50% level of the REFCLK rising edge * Pipeline mode * Non-pipeline mode PSDVAL setup time before the 50% level of the REFCLK rising edge * Pipeline mode * Non-pipeline mode TS setup time before the 50% level of the REFCLK rising edge BG setup time before the 50% level of the REFCLK rising edge Data bus setup time before the 50% level of the REFCLK rising edge in Normal * Pipeline mode * Non-pipeline mode Data bus setup time before the 50% level of the REFCLK rising edge in ECC and PARITY modes * Pipeline mode * Non-pipeline mode DP setup time before the 50% level of the REFCLK rising edge * Pipeline mode * Non-pipeline mode Address bus setup time before the 50% level of the REFCLK rising edge * Extra cycle mode (SIUBCR[EXDD] = 0) * Non-extra cycle mode (SIUBCR[EXDD] = 1) Address attributes: TT/TBST/TSIZ/GBL setup time before the 50% level of the REFCLK rising edge * Extra cycle mode (SIUBCR[EXDD] = 0) * Non-extra cycle mode (SIUBCR[EXDD] = 1) PUPMWAIT/IRQ signals Setup time before the 50% level of the REFCLK rising edge 1. 2.
Value2
0.5 3.5 5.0 4.0 3.5 4.0 4.0 3.0 3.5 3.5 5.0 4.5 2.5 5.0
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
11e
11f
11g 11h 12
13
2.5 8.0 4.0 9.0 5.0 8.0
ns ns ns ns ns ns
14
15a
15b
5.0 5.5 3.0
ns ns ns
161 Notes:
The setup time for these signals is for synchronous operation. Any setup time can be used for asynchronous operation. Input specifications are measured from the 50% level of the rising edge of REFCLK to the 50% level of the signal. Timings are measured at the pin.
2-14
AC Timings
Table 2-17. AC Timing for SIU Outputs
Maximum2 No.
31a
Characteristic
TA delay from the 50% level of the REFCLK rising edge * Pipeline mode * Non-pipeline mode TEA delay from the 50% level of the REFCLK rising edge * Pipeline mode * Non-pipeline mode PSDVAL delay from the 50% level of the REFCLK rising edge * Pipeline mode * Non-pipeline mode Address bus delay from the 50% level of the REFCLK rising edge * Multi master mode (SIUBCR[EBM] = 1) * Single master mode (SIUBCR[EBM] = 0) Address attributes: TT/TBST/TSIZ/GBL delay from the 50% level of the REFCLK rising edge BADDR delay from the 50% level of the REFCLK rising edge Data bus delay from the 50% level of the REFCLK rising edge * Pipeline mode * Non-pipeline mode DP delay from the 50% level of the REFCLK rising edge * Pipeline mode * Non-pipeline mode Memory controller signals/ALE delay from the 50% level of the REFCLK rising edge DBG/BR/DBB delay from the 50% level of the REFCLK rising edge AACK/ABB/CS delay from the 50% level of the REFCLK rising edge BG delay from the 50% level of the REFCLK rising edge TS delay from the 50% level of the REFCLK rising edge Delay from the 50% level of the REFCLK rising edge for all other signals 1.
Min. 30 pF
1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 5.0 4.0 3.0 3.5 4.0 3.5 6.3 5.5 5.5 3.5 5.0 6.0 4.0 6.5 5.5 4.0 4.5 4.0 3.5 4.5
Units 50 pF
6.5 5.5 4.5 5.0 5.5 5.0 7.8 7.0 7.0 5.0 6.5 7.5 5.5 8.0 7.0 5.5 6.0 5.5 5.0 6.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
31b
31c
32a
32b 32c 33a
33b
34 35a 35b 35c 35d 36
Notes:
2.
The maximum bus frequency depends on the mode: * In 60x-compatible mode connected to another MSC8103 device, the frequency is determined by adding the input and output longest timing values, which results in a frequency of 75 MHz for 30 pF output capacitance. In multi-master mode when connected to another MSC8103 device, the frequency is determined by adding the input and output longest timing values, which results in a frequency of 75 MHz for 30 pF output capacitance. * Certain bus modes, such as non-extra cycle (EXDD = 1), non-pipelined, and ECC/Parity modes, result in slower bus frequencies. * In single-master mode, the frequency depends on the timing of the devices connected to the MSC8103. Output specifications are measured from the 50% level of the rising edge of REFCLK to the 50% level of the signal. Timings are measured at the pin.
2-15
AC Timings
REFCLK 10 AACK/ARTRY/TA/TEA/DBG/BG/BR PSDVAL/ABB/DBB/TS inputs 11
10 12 Data bus inputs--normal mode 10 Data bus inputs--ECC and parity modes DP inputs Address bus/TT[0-4]/TC[0-2]/TBST/TSIZ[0-3]/GBL inputs PUPMWAIT/IRQn input 13 14 15 16 10
31 PSDVAL/TEA/TA outputs 32
Address bus/TT[0-4]/TC[0-2]/TBST/TSIZ[0-3]/GBL/BADDR[27-31] outputs
Data bus outputs DP outputs
33a
33b
Memory controller/ALE signals
34
35 AACK/ARTRY/ABB/TS/DBG/BG/BR/DBB/CS signals 36 All other normal mode outputs
Figure 2-6. Bus Signal Timing
2-16
AC Timings
2.7.4.2 DMA Data Transfers
Table 2-18 describes the DMA signal timing. Table 2-18. DMA Signals
Number
72 73 74 75 76
Characteristic
DREQ setup time before REFCLK falling edge DREQ hold time after REFCLK falling edge DONE setup time before REFCLK rising edge DONE hold time after REFCLK rising edge DACK/DRACK/DONE delay after REFCLK rising edge
Minimum
6 0.5 9 0.5 0.5
Maximum
-- -- -- -- 9
Units
ns ns ns ns ns
The DREQ signal is synchronized with the falling edge of REFCLK. DONE timing is relative to the rising edge of REFCLK. To achieve fast response, a synchronized peripheral should assert DREQ according to the timings in Table 2-18. Figure 2-7 shows synchronous peripheral interaction.
REFCLK 73 72 DREQ 75 74 DONE Input 76 DACK/DONE/DRACK Outputs
Figure 2-7. DMA Signals
2-17
AC Timings
2.7.5 HDI16 Signals
Table 2-19. Host Interface (HDI16) Timing1, 2
Number
44a 44b 44c
Characteristics3
Read data strobe minimum assertion HACK read minimum assertion width width4
Expression
(1.5 x TC) + 5.0 TC + 5.0 (2.5 x TC) + 5.0
Value
Note 11 Note 11 Note 11
Unit
ns ns ns
Read data strobe minimum deassertion width4 HACK read minimum deassertion width Read data strobe minimum deassertion width4 after "Last Data Register" reads5,6, or between two consecutive CVR, ICR, or ISR reads7 HACK minimum deassertion width after "Last Data Register" reads5,6 Write data strobe minimum assertion width8 HACK write minimum assertion width Write data strobe minimum deassertion width8 HACK write minimum deassertion width after ICR, CVR and Data Register writes5 Host data input minimum setup time before write data strobe deassertion8 Host data input minimum setup time before HACK write deassertion Host data input minimum hold time after write data strobe deassertion8 Host data input minimum hold time after HACK write deassertion Read data strobe minimum assertion to output data active from high impedance4 HACK read minimum assertion to output data active from high impedance Read data strobe maximum assertion to output data valid4 HACK read maximum assertion to output data valid Read data strobe maximum deassertion to output data high impedance4 HACK read maximum deassertion to output data high impedance Output data minimum hold time after read data strobe deassertion4 Output data minimum hold time after HACK read deassertion HCS[1-2] minimum assertion to read data strobe assertion4 HCS[1-2] minimum assertion to write data strobe assertion8 HCS[1-2] maximum assertion to output data valid HCS[1-2] minimum hold time after data strobe deassertion9 HA[0-3], HRW minimum setup time before data strobe assertion * Read * Write
9
45 46
(1.5 x TC) + 5.0
Note 11
ns
(2.5 x TC) + 5.0 --
Note 11 5.0
ns ns
47
48
--
5.0
ns
49
-- (2.0 x TC) + 5.0
5.0 Note 11
ns ns
50 51
--
5.0
ns
52
-- -- -- TC + 5.0 -- --
5.0 5.0 5.0 Note 11 0.0 0 5.0
ns ns ns ns ns ns ns ns ns ns ns ns
53 54 55 56 57
58 61 62 63 64
HA[0-3], HRW minimum hold time after data strobe deassertion9 Maximum delay from read data strobe deassertion to host request deassertion for "Last Data Register" read4, 5, 10 Maximum delay from write data strobe deassertion to host request deassertion for "Last Data Register" write5,8,10 Minimum delay from DMA HACK (OAD=0) or Read/Write data strobe(OAD=1) deassertion to HREQ assertion. Maximum delay from DMA HACK (OAD=0) or Read/Write data strobe(OAD=1) assertion to HREQ deassertion
-- (3.5 x TC) + 5.0 (3.0 x TC) + 5 (5.0 x TC) + 5.0 (3.5 x TC) + 5.0
5.0 Note 11 Note 11 Note 11 Note 11
2-18
AC Timings
Table 2-19. Host Interface (HDI16) Timing1, 2 (Continued)
Number
Notes: 1. 2.
Characteristics3
Expression
Value
Unit
TC = 1/ DSPCLK. At 300 MHz, T C = 3.3 ns In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable. 3. V CC = 3.3 V 0.3 V; TJ = -40C to +100 C, C L = 50 pF 4. The read data strobe is HRD/HRD in the dual data strobe mode and HDS/HDS in the single data strobe mode. 5. In 64-bit mode, The "last data register" is the register at address $7, which is the last location to be read or written in data transfers. This is RX0/TX0 in the little endian mode (HBE = 0), or RX3/TX3 in the big endian mode (HBE = 1). 6. This timing is applicable only if a read from the "last data register" is followed by a read from the RXL, RXM, or RXH registers without first polling RXDF or HREQ bits, or waiting for the assertion of the HREQ/HREQ signal. 7. This timing is applicable only if two consecutive reads from one of these registers are executed. 8. The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode. 9. The data strobe is host read (HRD/HRD) or host write (HWR/HWR) in the dual data strobe mode and host data strobe (HDS/HDS) in the single data strobe mode. 10. The host request is HREQ/HREQ in the single host request mode and HRRQ/HRRQ and HTRQ/HTRQ in the double host request mode. HRRQ/HRRQ is deasserted only when HOTX fifo is empty, HTRQ/HTRQ is deasserted only if HORX fifo is full (treat as level Host Request). 11. Compute the value using the expression.
Figure 2-8 and Figure 2-9 show HDI16 read signal timing. Figure 2-10 and Figure 2-11 show HDI16 write signal timing.
HA[0-3]
57 53 HCS[1-2] 57
58 56
58
HRW 44a HDS 44b 51 55 50 49 HD[0-15] 52 44c
61 HREQ (single host request) HRRQ (double host request)
Figure 2-8. Read Timing Diagram, Single Data Strobe
2-19
AC Timings
HA[0-3]
57 53 HCS[1-2] 44a HRD
58 56
44b 51 55 50 49 HD[0-15] 52 44a
61 HREQ (single host request) HRRQ (double host request)
Figure 2-9. Read Timing Diagram, Double Data Strobe
HA[0-3]
57 54 HCS[1-2] 57
58 56
58
HRW
45 HDS 46 47 48
HD[0-15]
HREQ (single host request) HTRQ (double host request)
62
Figure 2-10. Write Timing Diagram, Single Data Strobe
2-20
AC Timings
HA[0-3]
57 54 HCS[1-2]
58 56
45 HWR 46
47
48
HD[0-15]
HREQ (single host request) HTRQ (double host request)
62
Figure 2-11. Write Timing Diagram, Double Data Strobe
Figure 2-12 shows Host DMA read timing.
HREQ (Output)
64
63
44a RX[0-3] Read
44b
HACK
50
51
49 HD[0-15] (Output) Data Valid
52
Figure 2-12. Host DMA Read Timing Diagram, HPCR[OAD] = 0
2-21
AC Timings
Figure 2-13 shows Host DMA write timing.
HREQ (Output)
64 45 TX[0-3] Write 46
63
HACK
47 48 HD[0-15] (Output) Data Valid
Figure 2-13. Host DMA Write Timing Diagram, HPCR[OAD] = 0
2.7.6 CPM Timings
Table 2-20. CPM Input Characteristics
No.
39
Characteristic
FCC input setup time before low-to-high clock transition a. internal clock (BRGxO) b. external clock (serial clock input) FCC input hold time after low-to-high clock transition a. internal clock (BRGxO) b. external clock (serial clock input) SCC/SMC/SPI/I2C input setup time before low-to-high clock transition a. internal clock (BRGxO) b. external clock (serial clock input) SCC/SMC/SPI/I2C input hold time after low-to-high clock transition a. internal clock (BRGxO) b. external clock (serial clock input) TDM input setup time before low-to-high serial clock transition TDM input hold time after low-to-high serial transition PIO/TIMER/DMA input setup time before low-to-high serial clock transition PIO/TIMER/DMA input hold time after low-to-high serial clock transition FCC, SCC, SMC, SPI, I C are Non-Multiplexed Serial Interface signals.
2
Typical
10 5 0 3 20 5 0 5 5 5 10 3
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
17
18
19
20 21 22 23 Note:
2-22
AC Timings
Table 2-21. CPM Output Characteristics
No.
41
Characteristic
FCC output delay after low-to-high clock transition a. internal clock (BRGxO) b. external clock (serial input clock) SCC/SMC/SPI/I2C output delay after low-to-high clock transition a. internal clock (BRGxO) b. external clock (serial input clock) TDM output delay after low-to-high serial clock transition PIO/TIMER/DMA output delay after low-to-high serial clock transition FCC, SCC, SMC, SPI, I2 C are Non-Multiplexed Serial Interface signals.
Min
0 2 0 0 5 1
Max
6 18 20 30 15 14
Unit
ns ns ns ns ns ns
38
40 42 Note:
BRGxO 17a 39a FCC inputs 41a FCC outputs
Figure 2-14. FCC Internal Clock Diagram
Serial input clock 17b 39b FCC inputs 41b FCC outputs
Figure 2-15. FCC External Clock Diagram
BRGxO 19a 18a SCC/SMC/SPI/I2C inputs 38a SCC/SMC/SPI/I2C outputs
Figure 2-16. SCC/SMC/SPI/I2C Internal Clock Diagram
2-23
AC Timings
Serial input clock 19b 18b SCC/SMC/SPI/I2C inputs
38b SCC/SMCSPI/I2C outputs
Figure 2-17. SCC/SMC/SPI/I2C External Clock Diagram
Serial input clock 20 TDM inputs 21
40 TDM outputs
Figure 2-18. TDM Signal Diagram
REFCLK 23 22 PIO/TIMER/DMA inputs 42 PIO/TIMER/DMA outputs
Figure 2-19. PIO, Timer, and DMA Signal Diagram Note: The timing values refer to minimum system timing requirements. Actual implementation requires conformance to the specific protocol requirements. Refer to Chapter 1 to identify the specific input and output signals associated with the referenced internal controllers and supported communication protocols. For example, FCC1 supports ATM/Utopia operation in slave mode, multi-PHY master direct polling mode, and multi-PHY master multiplexed polling mode and each of these modes supports its own set of signals; the direction (input or output) of some of the shared signal names depends on the selected mode.
2-24
AC Timings
2.7.7 JTAG Signals
Table 2-22. JTAG Timing
All frequencies No.
500 501 502 503 508 509 510 511 512 513
Characteristics Min
TCK frequency of operation TCK cycle time TCK clock pulse width measured at 1.6 V TCK rise and fall times TMS, TDI data set-up time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO high impedance TRST assert time TRST set-up time to TCK low 0.0 25.0 12.5 0.0 6.0 3.0 0.0 0.0 100.0 40.0
Unit Max
40.0 -- -- 3.0 -- -- 15.0 20.0 -- -- MHz ns ns ns ns ns ns ns ns ns
501 502 TCK (Input) VIH VIL 503 503 VM 502 VM
Figure 2-20. Test Clock Input Timing Diagram
TCK (Input) VIH VIL 508 TDI TMS (Input) 510 TDO (Output) 511 TDO (Output) 510 TDO (Output) Input Data Valid 509
Output Data Valid
Output Data Valid
Figure 2-21. Test Access Port Timing Diagram
2-25
AC Timings
TCK (Input) 513 TRST (Input) 512
Figure 2-22. TRST Timing Diagram
2-26
Chapter 3
Packaging
3.1 Pin-Out and Package Information
This sections provides information about the MSC8103 package, including diagrams of the package pinouts and tables showing how the signals discussed in Chapter 1 are allocated. The MSC8103 is available in a 332-pin lidded Flip Chip-Plastic Ball Grid Array (FC-PBGA).
3.2 Lidded FC-PBGA Package Description
Figure 3-1 and Figure 3-2 show top and bottom views of the FC-PBGA package, including pinouts. Table 3-1 lists the MSC8103 signals alphabetically by signal name. Connections with multiple names are listed individually by each name. Signals with programmable polarity are shown both as signals which are asserted low (default) and high (that is, NAME/NAME). Table 3-2 lists the signals numerically by pin number. Each pin number is listed once with the various signals that are multiplexed to it. For simplicity, signals with programmable polarity are shown in this table only with their default name (asserted low).
3-1
Lidded FC-PBGA Package Description
Top View
1 A 2 IRQ5 3 D1 4 D4 5 D7 6 D11 7 D17 8 D22 9 D27 10 D32 11 D37 12 D42 13 D46 14 D51 15 D55 16 D60 17 D62 18 D63 19 A
B
IRQ1
IRQ3
D0
D3
D6
D10
D16
D21
D26
D31
D36
D41
D45
D50
D54
D59
PWE6
DBG
BADDR B 28 BADDR C 29 BADDR D 27 PSD CAS E
C THERM DP0 1
IRQ4
D2
D5
D9
D15
D20
D25
D30
D35
D40
D44
D49
D53
D58
D61
DBB
D
EE1
EE0
THERM 2
IRQ2
IRQ6
D8
D14
D19
D24
D29
D34
D39
D43
D48
D52
D57
PWE5
GBL
E
EE4
EE3
EE2
VDDH
VDD
VDDH
D13
VDDH
VDD
VDDH
VDDH
VDD
VDDH
D47
VDDH
D56
PSDA 10 PWE7
MOD CK1
F
TDO
EED
EE5
VDD
GND
IRQ7
GND
D18
GND
D28
GND
D38
GND
PSD WE
GND
VDD
MOD CK2 MOD CK3
BCTL0 F
G
PA31
TMS
TRST
TCK
VDDH
GND
D12
GND
D23
GND
D33
GND
PSD VAL
GND
VDDH
VDDH
TEA
POE
G
H
PB30
PD31
PC31
PB31
GND
TDI
GND
BADDR BADDR 31 30
GND
VDD
BR
ALE
PWE4
H
03 81 SC M
J
PA29
PD30
PC30
VDD
GND
GND
PA30
TA
GND
VDDH
VDDH
PSDA MUX
PGTA
PWE3
J
K
PA28
PD29
PC29
PB29
VDDH
GND
GND
GND
PWE2
GND
VDDH
PWE1
PWE0
CS2
K
L
PA27
PB28
PC28
VDD
GND
GND
PC27
CS6
GND
GND
VDD
CS1
CS3
BCTL1
L
M
PB27
PC26
PB26
VDDH
GND
PA26
PA16
A21
A26
GND
CS0
CS5
CS7
CS4
M
N
PC25
PA25
PB25
VDD
PC23
GND
PD17
CLKIN
GND
PC6
TSIZ3
TT1
TT0
A1
VDDH
VDDH
A28
A30
A31
N
P
PC24
PA24
PB24
PA23
PB20
GND
GND
DLL_IN
GND
PC4
GND
GND
GND
GND
GND
VDD
A23
A27
A29
P
R
PC22
SPARE 1 PB22
PA22
PB18
PA19
VDDH
VDDH
VDD
VDDH
VDDH
VDD
VDDH
VDD
VDDH
VDDH
A15
A19
A24
A25
R
T
PB21
PA20
PA17
PC13
PC14
VCC SYN1 GND SYN1 GND SYN
CLK OUT
PA12
PC7
PA6
AACK
TS
A3
VDDH
A12
A16
A20
A22
T
U
PA21
PB19
PD18
PD16
NMI
RST CONF
PA13
PA10
PA8
SPARE ARTRY TBST 5 ABB BG TSIZ0
TT2
A4
A8
A11
A17
A18
U
V
PB23
PD19
PC15
PC12
NMI_ OUT
HRESET
PA11
PD7
PA7
TT3
A2
A6
A9
A13
A14
V
W 1
PA18 2
PA15 3
SRESET
PO RESET TEST 5 6
VCC SYN 7
PA14 8
PA9 9
PC5 10
INT _OUT 11
TSIZ2 12
TSIZ1 13
TT4 14
A0 15
A5 16
A7 17
A10 18 19
W
4
Note: Signal names in this figure are the default signals after reset, except for signals C2, C19, D1, D2, D18, E1, F3, H13, H14, and W11 which show the second configuration signal name.
Figure 3-1. MSC8103 Flip Chip Plastic Ball Grid Array (FC-PBGA), Top View
3-2
Lidded FC-PBGA Package Description
Bottom View
19 A 18 D63 17 D62 16 D60 15 D55 14 D51 13 D46 12 D42 11 D37 10 D32 9 D27 8 D22 7 D17 6 D11 5 D7 4 D4 3 D1 2 IRQ5 1 A
B BADDR 28
DBG
PWE6
D59
D54
D50
D45
D41
D36
D31
D26
D21
D16
D10
D6
D3
D0
IRQ3
IRQ1
B
C BADDR 29
DBB
D61
D58
D53
D49
D44
D40
D35
D30
D25
D20
D15
D9
D5
D2
IRQ4
DP0
THERM C 1
D BADDR 27 PSD CAS
GBL
PWE5
D57
D52
D48
D43
D39
D34
D29
D24
D19
D14
D8
IRQ6
IRQ2
THERM 2
EE0
EE1
D
E
MOD CK1
PSDA 10
D56
VDDH
D47
VDDH
VDD
VDDH
VDDH
VDD
VDDH
D13
VDDH
VDD
VDDH
EE2
EE3
EE4
E
F BCTL0
MOD CK2
PWE7
VDD
GND
PSD WE
GND
D38
GND
D28
GND
D18
GND
IRQ7
GND
VDD
EE5
EED
TDO
F
G
POE
MOD CK3
TEA
VDDH
VDDH
GND
PSD VAL
GND
D33
GND
D23
GND
D12
GND
VDDH
TCK
TRST
TMS
PA31
G
H
PWE4
ALE
BR
VDD
GND
BADDR BADDR 30 31
GND
TDI
GND
PB31
PC31
PD31
PB30
H
PWE3
VDDH
VDDH
M SC 81 03
J
PGTA
PSDA MUX
GND
TA
PA30
GND
GND
VDD
PC30
PD30
PA29
J
K
CS2
PWE0
PWE1
VDDH
GND
PWE2
GND
GND
GND
VDDH
PB29
PC29
PD29
PA28
K
L
BCTL1
CS3
CS1
VDD
GND
GND
CS6
PC27
GND
GND
VDD
PC28
PB28
PA27
L
M
CS4
CS7
CS5
CS0
GND
A26
A21
PA16
PA26
GND
VDDH
PB26
PC26
PB27
M
N
A31
A30
A28
VDDH
VDDH
A1
TT0
TT1
TSIZ3
PC6
GND
CLKIN
PD17
GND
PC23
VDD
PB25
PA25
PC25
N
P
A29
A27
A23
VDD
GND
GND
GND
GND
GND
PC4
GND
DLL_IN
GND
GND
PB20
PA23
PB24
PA24
PC24
P
R
A25
A24
A19
A15
VDDH
VDDH
VDD
VDDH
VDD
VDDH
VDDH
VDD
VDDH
VDDH
PA19
PB18
PA22
SPARE 1
PC22
R
T
A22
A20
A16
A12
VDDH
A3
TS
AACK
PA6
PC7
PA12
CLK OUT
VCC SYN1
PC14
PC13
PA17
PA20
PB22
PB21
T
U
A18
A17
A11
A8
A4
TT2
TBST
ARTRY SPARE 5 ABB
PA8
PA10
PA13
GND SYN1 GND SYN
RST CONF
NMI
PD16
PD18
PB19
PA21
U
V
A14
A13
A9
A6
A2
TT3
TSIZ0
BG
PA7
PD7
PA11
HRESET
NMI_ OUT PO RESET 5
PC12
PC15
PD19
PB23
V
W
A10 19 18
A7 17
A5 16
A0 15
TT4 14
TSIZ1 13
TSIZ2 12
INT _OUT 11
PC5 10
PA9 9
PA14 8
VCC SYN 7
TEST 6
SRESET
PA15 3
PA18 2 1
W
4
Note: Signal names in this figure are the default signals after reset, except for signals C2, C19, D1, D2, D18, E1, F3, H13, H14, and W11 which show the second configuration signal name.
Figure 3-2. MSC8103 Flip Chip Plastic Ball Grid Array (FC-PBGA), Bottom Vie 3-3
Lidded FC-PBGA Package Description
Table 3-1. MSC8103 Signal Listing By Name
Signal Name
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 AACK
Number
W15 N14 V15 T14 U15 W16 V16 W17 U16 V17 W18 U17 T16 V18 V19 R16 T17 U18 U19 R17 T18 M13 T19 P17 R18 R19 M14 P18 N17 P19 N18 N19 T12
3-4
Lidded FC-PBGA Package Description
Table 3-1. MSC8103 Signal Listing By Name (Continued)
Signal Name
ABB ALE ARTRY BADDR27 BADDR28 BADDR29 BADDR30 BADDR31 BCTL0 BCTL1 BG BNKSEL0 BNKSEL1 BNKSEL2 BR BRG1O BRG1O BRG2O BRG2O BRG3O BRG4O BRG5O BRG6O BRG7O BRG8O BTM0 BTM1 CD for FCC1 CD for FCC2 CD/RENA for SCC1 CD/RENA for SCC2 CLK1 CLK2
Number
V11 H18 U12 D19 B19 C19 H14 H13 F19 L19 V12 E18 F18 G18 H17 H3 V2 J3 N7 K3 L3 L7 M2 N1 P1 E1 F3 N10 P10 T6 V4 H3 J3
3-5
Lidded FC-PBGA Package Description
Table 3-1. MSC8103 Signal Listing By Name (Continued)
Signal Name
CLK3 CLK4 CLK5 CLK6 CLK7 CLK8 CLK9 CLK10 CLKIN CLKOUT COL for FCC1 COL for FCC2 CRS for FCC1 CRS for FCC2 CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 CTS for FCC1 CTS for FCC2 CTS/CLSN for SCC1 CTS/CLSN for SCC1 CTS/CLSN for SCC2 CTS/CLSN for SCC2 D0 D1 D2 D3 D4
Number
K3 L3 L7 M2 N1 P1 N5 R1 N8 T8 G1 M1 J7 M3 M16 L17 K19 L18 M19 M17 L13 M18 T10 W10 K3 V3 L3 T5 B3 A3 C4 B4 A4
3-6
Lidded FC-PBGA Package Description
Table 3-1. MSC8103 Signal Listing By Name (Continued)
Signal Name
D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37
Number
C5 B5 A5 D6 C6 B6 A6 G7 E7 D7 C7 B7 A7 F8 D8 C8 B8 A8 G9 D9 C9 B9 A9 F10 D10 C10 B10 A10 G11 D11 C11 B11 A11
3-7
Lidded FC-PBGA Package Description
Table 3-1. MSC8103 Signal Listing By Name (Continued)
Signal Name
D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 DACK1 DACK2 DACK3 DACK4 DBB DBG DBREQ
Number
F12 D12 C12 B12 A12 D13 C13 B13 A13 E14 D14 C14 B14 A14 D15 C15 B15 A15 E16 D16 C16 B16 A16 C17 A17 A18 N5 N1 D5 F6 C18 B18 D2
3-8
Lidded FC-PBGA Package Description
Table 3-1. MSC8103 Signal Listing By Name (Continued)
Signal Name
DLLIN DP0 DP1 DP2 DP3 DP4 DP5 DP6 DP7 DRACK1/DONE1 DRACK2/DONE2 DREQ1 DREQ2 DREQ3 DREQ4 EE0 EE1 EE2 EE3 EE4 EE5 EED EXT_BG2 EXT_BG3 EXT_BR2 EXT_BR3 EXT_DBG2 EXT_DBG3 EXT1 EXT2 GBL GND GND
Number
P8 C2 B1 D4 B2 C3 A2 D5 F6 H2 J2 R1 P1 C3 A2 D2 D1 E3 E2 E1 F3 F2 B1 C3 C2 B2 D4 A2 H3 N5 D18 F11 F13
3-9
Lidded FC-PBGA Package Description
Table 3-1. MSC8103 Signal Listing By Name (Continued)
Signal Name
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
Number
F15 F5 F7 F9 G10 G12 G14 G6 G8 H15 H5 H7 J14 J5 J6 K13 K15 K6 K7 L14 L15 L5 L6 M15 M5 N6 N9 P11 P12 P13 P14 P15 P6
3-10
Lidded FC-PBGA Package Description
Table 3-1. MSC8103 Signal Listing By Name (Continued)
Signal Name
GND GND GNDSYN GNDSYN1 H8BIT HA0 HA1 HA2 HA3 HACK/HACK HCS1/HCS1 HCS2/HCS2 HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9 HD10 HD11 HD12 HD13 HD14 HD15 HDDS HDS/HDS HDSP HPE HRD/HRD
Number
P7 P9 V7 U7 B16 D14 C14 B14 A14 E16 D15 A16 A10 G11 D11 C11 B11 A11 F12 D12 C12 B12 A12 D13 C13 B13 A13 E14 C16 B15 D16 D1 C15
3-11
Lidded FC-PBGA Package Description
Table 3-1. MSC8103 Signal Listing By Name (Continued)
Signal Name
HREQ/HREQ HRESET HRRQ/HRRQ HRW HTRQ/HTRQ HWR/HWR INT_OUT IRQ1 IRQ1 IRQ2 IRQ2 IRQ2 IRQ3 IRQ3 IRQ3 IRQ4 IRQ5 IRQ5 IRQ6 IRQ7 IRQ7 L1RSYNC for SI1 TDMA1 L1RSYNC for SI2 TDMB2 L1RSYNC for SI2 TDMC2 L1RSYNC for SI2 TDMD2 L1RXD for SI1 TDMA1 Serial L1RXD for SI2 TDMB2 L1RXD for SI2 TDMC2 L1RXD for SI2 TDMD2 L1RXD0 for SI1 TDMA1 Nibble L1RXD1 for SI1 TDMA1 Nibble L1RXD2 for SI1 TDMA1 Nibble L1RXD3 for SI1 TDMA1 Nibble
Number
A15 V6 E16 C15 A15 B15 W11 B1 D18 C19 D4 V11 B2 C18 H14 C3 A2 H13 D5 F6 W11 T11 K4 P3 P5 U10 H1 M3 T2 U10 T2 V1 P3
3-12
Lidded FC-PBGA Package Description
Table 3-1. MSC8103 Signal Listing By Name (Continued)
Signal Name
L1TSYNC for SI1 TDMA1 L1TSYNC for SI2 TDMB2 L1TSYNC for SI2 TDMC2 L1TSYNC for SI2 TDMD2 L1TXD for SI1 TDMA1 Serial L1TXD for SI2 TDMB2 L1TXD for SI2 TDMC2 L1TXD for SI2 TDMD2 L1TXD0 for SI1 TDMA1 Nibble L1TXD1 for SI1 TDMA1 Nibble L1TXD2 for SI1 TDMA1 Nibble L1TXD3 for SI1 TDMA1 Nibble LIST1 for SI1 LIST1 for SI2 LIST2 for SI1 LIST2 for SI2 LIST3 for SI1 LIST3 for SI2 LIST4 for SI1 LIST4 for SI2 MODCK1 MODCK2 MODCK3 MSNUM0 MSNUM1 MSNUM2 MSNUM3 MSNUM4 MSNUM5 NMI NMI_OUT PA6 PA7
Number
V10 L2 N3 T1 W9 H4 M1 V1 W9 P5 T1 N3 R1 T10 T6 N10 V4 W10 T5 P10 E18 F18 G18 N2 P2 U8 T9 V8 U9 U5 V5 T11 V10
3-13
Lidded FC-PBGA Package Description
Table 3-1. MSC8103 Signal Listing By Name (Continued)
Signal Name
PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26
Number
U10 W9 U9 V8 T9 U8 W8 W3 M7 T4 W2 R5 T3 U1 R3 P4 P2 N2 M6 L1 K1 J1 J7 G1 R4 U2 P5 T1 T2 V1 P3 N3 M3
3-14
Lidded FC-PBGA Package Description
Table 3-1. MSC8103 Signal Listing By Name (Continued)
Signal Name
PB27 PB28 PB29 PB30 PB31 PBS0 PBS1 PBS2 PBS3 PBS4 PBS5 PBS6 PBS7 PC4 PC5 PC6 PC7 PC12 PC13 PC14 PC15 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 PD7 PD16
Number
M1 L2 K4 H1 H4 K18 K17 K14 J19 H19 D17 B17 F17 P10 W10 N10 T10 V4 T5 T6 V3 R1 N5 P1 N1 M2 L7 L3 K3 J3 H3 V9 U4
3-15
Lidded FC-PBGA Package Description
Table 3-1. MSC8103 Signal Listing By Name (Continued)
Signal Name
PD17 PD18 PD19 PD29 PD30 PD31 PGPL0 PGPL1 PGPL2 PGPL3 PGPL4 PGPL5 PGTA POE PORESET PPBS PSDA10 PSDAMUX PSDCAS PSDDQM0 PSDDQM1 PSDDQM2 PSDDQM3 PSDDQM4 PSDDQM5 PSDDQM6 PSDDQM7 PSDRAS PSDVAL PSDWE PUPMWAIT PWE0 PWE1
Number
N7 U3 V2 K2 J2 H2 E17 F14 G19 E19 J18 J17 J18 G19 W5 J18 E17 J17 E19 K18 K17 K14 J19 H19 D17 B17 F17 G19 G13 F14 J18 K18 K17
3-16
Lidded FC-PBGA Package Description
Table 3-1. MSC8103 Signal Listing By Name (Continued)
Signal Name
PWE2 PWE3 PWE4 PWE5 PWE6 PWE7 Reserved Reserved Reserved Reserved Reserved Reserved Reserved RSTCONF RTS for FCC1 RTS for FCC2 RTS/TENA for SCC1 RTS/TENA for SCC2 RX_DV for FCC1 RX_DV for FCC2 RX_ER for FCC1 RX_ER for FCC2 RXADDR0 for FCC1 UTOPIA 8 RXADDR1 for FCC1 UTOPIA 8 RXADDR2 for FCC1 UTOPIA 8 RXADDR2/RXCLAV1 for FCC1 UTOPIA 8 RXADDR3 for FCC1 UTOPIA 8 RXADDR4 for FCC1 UTOPIA 8 RXCLAV for FCC1 UTOPIA 8 RXCLAV0 for FCC1 UTOPIA 8 RXCLAV2 for FCC1 UTOPIA 8 RXCLAV3 for FCC1 UTOPIA 8 RXD for FCC1 transparent/HDLC serial
Number
K14 J19 H19 D17 B17 F17 A17 A18 C2 C17 C19 H14 H13 U6 J7 L2 K2 L2 L1 H1 M6 L2 T6 V4 N10 N10 K2 U3 M6 M6 K2 V4 T4
3-17
Lidded FC-PBGA Package Description
Table 3-1. MSC8103 Signal Listing By Name (Continued)
Signal Name
RXD for FCC2 transparent/HDLC serial RXD for SCC1 RXD for SCC2 RXD0 for FCC1 MII/HDLC nibble RXD0 for FCC1 UTOPIA 8 RXD0 for FCC2 MII/HDLC nibble RXD1 for FCC1 MII/HDLC nibble RXD1 for FCC1 UTOPIA 8 RXD1 for FCC2 MII/HDLC nibble RXD2 for FCC1 MII/HDLC nibble RXD2 for FCC1 UTOPIA 8 RXD2 for FCC2 MII/HDLC nibble RXD3 for FCC1 MII/HDLC nibble RXD3 for FCC1 UTOPIA 8 RXD3 for FCC2 MII/HDLC nibble RXD4 for FCC1 UTOPIA 8 RXD5 for FCC1 UTOPIA 8 RXD6 for FCC1 UTOPIA 8 RXD7 for FCC1 UTOPIA 8 RXENB for FCC1 RXPRTY for FCC1 UTOPIA 8 RXSOC for FCC1 SCL SDA SMRXD for SMC1 SMRXD for SMC2 SMSYN for SMC1 SMSYN for SMC2 SMTXD for SMC1 SMTXD for SMC2 SMTXD for SMC2 SPARE1 SPARE5
Number
T1 H2 H4 T4 U9 T1 M7 V8 P5 W3 T9 U2 W8 U8 R4 W8 W3 M7 T4 K1 N7 L1 R4 U2 P10 U10 V9 V10 W10 W9 V3 R2 U11
3-18
Lidded FC-PBGA Package Description
Table 3-1. MSC8103 Signal Listing By Name (Continued)
Signal Name
SPICLK SPIMISO SPIMOSI SPISEL SRESET TA TBST TC0 TC1 TC2 TCK TDI TDO TEA TEST TGATE1 TGATE2 THERM1 THERM2 TIN1/TOUT2 TIN2 TIN3/TOUT4 TIN4 TMCLK TMS TOUT1 TOUT3 TRST TS TSIZ0 TSIZ1 TSIZ2 TSIZ3
Number
U3 U4 N7 V2 W4 J13 U13 E18 F18 G18 G4 H6 F1 G17 W6 H3 L7 C1 D3 L3 K3 P1 N1 M2 G2 J3 M2 G3 T13 V13 W13 W12 N11
3-19
Lidded FC-PBGA Package Description
Table 3-1. MSC8103 Signal Listing By Name (Continued)
Signal Name
TT0 TT1 TT2 TT3 TT4 TX_EN for FCC1 MII TX_EN for FCC2 MII TX_ER for FCC1 MII TX_ER for FCC2 MII TXADDR0 for FCC1 UTOPIA 8 TXADDR1 for FCC1 UTOPIA 8 TXADDR2 for FCC1 UTOPIA 8 TXADDR2 for FCC1 UTOPIA 8 TXADDR3 for FCC1 UTOPIA 8 TXADDR4 for FCC1 UTOPIA 8 TXCLAV for FCC1 UTOPIA 8 TXCLAV0 for FCC1 UTOPIA 8 TXCLAV1 for FCC1 UTOPIA 8 TXCLAV2 for FCC1 UTOPIA 8 TXCLAV3 for FCC1 UTOPIA 8 TXD for FCC1 transparent/HDLC serial TXD for FCC2 transparent/HDLC serial TXD for SCC1 TXD for SCC2 TXD0 for FCC1 MII/HDLC nibble TXD0 for FCC1 UTOPIA 8 TXD0 for FCC2 MII/HDLC nibble TXD1 for FCC1 MII/HDLC nibble TXD1 for FCC1 UTOPIA 8 TXD1 for FCC2 MII/HDLC nibble TXD2 for FCC1 MII/HDLC nibble TXD2 for FCC1 UTOPIA 8 TXD2 for FCC2 MII/HDLC nibble
Number
N13 N12 U14 V14 W14 K1 K4 J1 H4 V3 T5 T10 T10 V9 V2 J7 J7 T10 V9 V2 W2 T2 J2 H1 W2 N2 T2 R5 P2 V1 T3 P4 P3
3-20
Lidded FC-PBGA Package Description
Table 3-1. MSC8103 Signal Listing By Name (Continued)
Signal Name
TXD3 for FCC1 MII/HDLC nibble TXD3 for FCC1 UTOPIA 8 TXD3 for FCC2 MII/HDLC nibble TXD4 for FCC1 UTOPIA 8 TXD5 for FCC1 UTOPIA 8 TXD6 for FCC1 UTOPIA 8 TXD7 for FCC1 UTOPIA 8 TXENB for FCC1 TXPRTY for FCC1 UTOPIA 8 TXSOC for FCC1 VCCSYN VCCSYN1 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDH VDDH VDDH VDDH VDDH VDDH VDDH
Number
U1 R3 N3 U1 T3 R5 W2 G1 U4 J1 W7 T7 E12 E5 E9 F16 F4 H16 J4 L16 L4 N4 P16 R11 R13 R8 E10 E11 E13 E15 E4 E6 E8
3-21
Lidded FC-PBGA Package Description
Table 3-1. MSC8103 Signal Listing By Name (Continued)
Signal Name
VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH
Number
G15 G16 G5 J15 J16 K16 K5 M4 N15 N16 R10 R12 R14 R15 R6 R7 R9 T15
Table 3-2. MSC8103 Signal Listing by Pin Designator
Number
A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14
Signal Name
IRQ5 / DP5 / DREQ4 / EXT_DBG3 D1 D4 D7 D11 D17 D22 D27 D32 / HD0 D37 / HD5 D42 / HD10 D46 / HD14 D51 / HA3
3-22
Lidded FC-PBGA Package Description
Table 3-2. MSC8103 Signal Listing by Pin Designator (Continued)
Number
A15 A16 A17 A18 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15
Signal Name
D55 / HREQ / HTRQ D60 / HCS2 D62 / Reserved D63 / Reserved IRQ1 / DP1 / EXT_BG2 IRQ3 / DP3 / EXT_BR3 D0 D3 D6 D10 D16 D21 D26 D31 D36 / HD4 D41 / HD9 D45 / HD13 D50 / HA2 D54 / HDS / HWR D59 / H8BIT PWE6 / PSDDQM6 / PBS6 DBG BADDR28 THERM1 Reserved / DP0 / EXT_BR2 IRQ4 / DP4 / DREQ3 / EXT_BG3 D2 D5 D9 D15 D20 D25 D30 D35 / HD3 D40 / HD8 D44 / HD12 D49 / HA1 D53 / HRW / HRD
3-23
Lidded FC-PBGA Package Description
Table 3-2. MSC8103 Signal Listing by Pin Designator (Continued)
Number
C16 C17 C18 C19 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15
Signal Name
D58 / HDDS D61 DBB / IRQ3 BADDR29 / IRQ2 HPE / EE1 DBREQ / EE0 THERM2 IRQ2 / DP2 / EXT_DBG2 IRQ6 / DP6 / DACK3 D8 D14 D19 D24 D29 D34 / HD2 D39 / HD7 D43 / HD11 D48 / HA0 D52 / HCS1 D57 / HDSP PWE5 / PSDDQM5 / PBS5 IRQ1 / GBL BADDR27 BTM0 / EE4 EE3 EE2 VDDH VDD VDDH D13 VDDH VDD VDDH VDDH VDD VDDH D47 / HD15 VDDH
3-24
Lidded FC-PBGA Package Description
Table 3-2. MSC8103 Signal Listing by Pin Designator (Continued)
Number
E16 E17 E18 E19 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15
Signal Name
D56 / HACK / HRRQ PSDA10 / PGPL0 MODCK1 / TC0 / BNKSEL0 PSDCAS / PGPL3 TDO EED BTM1 / EE5 VDD GND IRQ7 / DP7 / DACK4 GND D18 GND D28 GND D38 / HD6 GND PSDWE / PGPL1 GND VDD PWE7 / PSDDQM7 / PBS7 MODCK2 / TC1 / BNKSEL1 BCTL0 PA31 / FCC1:UTOPIA8:TXENB / FCC1:MII:COL TMS TRST TCK VDDH GND D12 GND D23 GND D33 / HD1 GND PSDVAL GND VDDH
3-25
Lidded FC-PBGA Package Description
Table 3-2. MSC8103 Signal Listing by Pin Designator (Continued)
Number
G16 G17 G18 G19 H1 H2 H3 H4 H5 H6 H7 H13 H14 H15 H16 H17 H18 H19 J1 J2 J3 J4 J5 J6 J7 J13 J14 J15 J16 J17 J18 J19 K1 K2 K3 K4
Signal Name
VDDH TEA MODCK3 / TC2 / BNKSEL2 POE / PSDRAS / PGPL2 PB30 / FCC2:MII:RX_DV / SCC2:TXD / TDBM2:L1RXD PD31 / SCC1:RXD / DRACK1 / DONE1 PC31 / BRG1O / CLK1 / TGATE1 PB31 / FCC2:MII:TX_ER / SCC2:RXD / TDMB2:L1TXD GND TDI GND Reserved / BADDR31 / IRQ5 Reserved / BADDR30 / IRQ3 GND VDD BR ALE PWE4 / PSDDQM4 / PBS4 PA29 / FCC1:UTOPIA8:TXSOC / FCC1:MII:TX_ER PD30 / SCC1:TXD / DMA:DRACK2/DONE2 PC30 / EXT1 / BRG2O / CLK2 / TOUT1 VDD GND GND PA30 / FCC1:UTOPIA8:TXCLAV / FCC1:UTOPIA8:TXCLAV0 / FCC1:MII:CRS / FCC1:HDLC and transparent:RTS TA GND VDDH VDDH PSDAMUX / PGPL5 PGTA / PUPMWAIT / PPBS / PGPL4 PWE3 / PSDDQM3 / PBS3 PA28 / FCC1:UTOPIA8:RXENB / FCC1:MII:TX_EN PD29 / FCC1:UTOPIA8:RXADDR3 / FCC1:UTOPIA8:RXCLAV2 / SCC1:RTS/TENA PC29 / SCC1:CTS / SCC1:CLSN / BRG3O / CLK3 / TIN2 PB29 / FCC2:MII:TX_EN / TDMB2:L1RSYNC
3-26
Lidded FC-PBGA Package Description
Table 3-2. MSC8103 Signal Listing by Pin Designator (Continued)
Number
K5 K6 K7 K13 K14 K15 K16 K17 K18 K19 L1 L2 L3 L4 L5 L6 L7 L13 L14 L15 L16 L17 L18 L19 M1 M2 M3 M4 M5 M6 M7 M13 M14 M15 M16 M17 M18
Signal Name
VDDH GND GND GND PWE2 / PSDDQM2 / PBS2 GND VDDH PWE1 / PSDDQM1 / PBS1 PWE0 / PSDDQM0 / PBS0 CS2 PA27 / FCC1:UTOPIA8:RXSOC / FCC1:MII:RX_DV PB28 / FCC2:RX_ER / FCC2:HDLC:RTS / SCC2:RTS/TENA / TDMB2:L1TSYNC PC28 / SCC2:CTS/CLSN / BRG4O / CLK4 / TIN1/TOUT2 VDD GND GND PC27 / CLK5 / BRG5O / TGATE2 CS6 GND GND VDD CS1 CS3 BCTL1 PB27 / FCC2:MII:COL / TDMC2:L1TXD PC26 / TMCLK / BRG6O / CLK6 / TOUT3 PB26 / FCC2:MII:CRS / TDMC2:L1RXD VDDH GND PA26 / FCC1:UTOPIA8:RXCLAV / FCC1:UTOPIA8:RXCLAV0 / FCC1:MII:RX_ER PA16 / FCC1:UTOPIA8:RXD6 / FCC1:MII and HDLC nibble:RXD1 A21 A26 GND CS0 CS5 CS7
3-27
Lidded FC-PBGA Package Description
Table 3-2. MSC8103 Signal Listing by Pin Designator (Continued)
Number
M19 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15
Signal Name
CS4 PC25 / DMA:DACK2 / BRG7O / CLK7 / TIN4 PA25 / FCC1:UTOPIA8:TXD0 / SDMA:MSNUM0 PB25 / FCC2:MII and HDLC nibble:TXD3 / TDMA1:nibble:L1TXD3 / TDMC2:L1TSYNC VDD PC23 / EXT2 / DMA:DACK1 / CLK9 GND PD17 / FCC1:UTOPIA8:RXPRTY / SPI:SPIMOSI / BRG2O CLKIN GND PC6 / FCC1:UTOPIA8:RXADDR2 / FCC1:UTOPIA8:RXADDR2/RXCLAV1 / FCC1:CD / SI2:LIST2 TSIZ3 TT1 TT0 A1 VDDH VDDH A28 A30 A31 PC24 / DMA:DREQ2 / BRG8O / CLK8 / TIN3/TOUT4 PA24 / FCC1:UTOPIA8:TXD1 / SDMA:MSNUM1 PB24 / FCC2:MII and HDLC nibble:TXD2 / TDMA1:nibble:L1RXD3 / TDMC2:L1RSYNC PA23 / FCC1:UTOPIA8:TXD2 PB20 / FCC2:MII and HDLC nibble:RXD1 / TDMA1:nibble:L1TXD1 / TDMD2:L1RSYNC GND GND DLLIN GND PC4 / FCC2:CD / SMC1:SMRXD / SI2:LIST4 GND GND GND GND GND
3-28
Lidded FC-PBGA Package Description
Table 3-2. MSC8103 Signal Listing by Pin Designator (Continued)
Number
P16 P17 P18 P19 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 T1
Signal Name
VDD A23 A27 A29 PC22 / SI1:LIST1 / DREQ1 / CLK10 SPARE1 PA22 / FCC1:UTOPIA8:TXD3 PB18 / FCC2:MII and HDLC nibble:RXD3 / I2C:SCL PA19 / FCC1:UTOPIA8:TXD6 / FCC1:MII and HDLC nibble:TXD1 VDDH VDDH VDD VDDH VDDH VDD VDDH VDD VDDH VDDH A15 A19 A24 A25 PB21 / FCC2:MII and HDLC nibble:RXD0 / FCC2:transparent and HDLC serial:RXD /TDMA1:nibble:L1TXD2 / TDMD2:L1TSYNC PB22 / FCC2:MII and HDLC nibble TXD0 / FCC2:transparent and HDLC serial TXD /TDMA1:nibble L1RXD1 / TDMD2:L1RXD PA20 / FCC1:UTOPIA8 TXD5 / FCC1:MII and HDLC nibble TXD2 PA17 / FCC1:UTOPIA8 RXD7 / FCC1:MII and HDLC nibble RXD0 / FCC1:transparent and HDLC serial RXD PC13 / FCC1:UTOPIA8:TXADDR1 / SCC2:CTS/CLSN / SI1:LIST4 PC14 / FCC1:UTOPIA8:RXADDR0 / SCC1:CD/RENA / SI1:LIST2 V CCSYN1 CLKOUT PA12 / FCC1:UTOPIA8:RXD2 / SDMA:MSNUM3 PC7 / FCC1:UTOPIA8:TXADDR2 / FCC1:UTOPIA8:TXADDR2/TXCLAV1 / FCC1:CTS / SI1:LIST1 PA6 / TDMA1:L1RSYNC
T2
T3 T4 T5 T6 T7 T8 T9 T10 T11
3-29
Lidded FC-PBGA Package Description
Table 3-2. MSC8103 Signal Listing by Pin Designator (Continued)
Number
T12 T13 T14 T15 T16 T17 T18 T19 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 V1 V2 V3 V4 V5 V6 V7 V8 V9
Signal Name
AACK TS A3 VDDH A12 A16 A20 A22 PA21 / FCC1:TXD4 / FCC1:MII and HDLC nibble TXD3 PB19 / FCC2:MII and HDLC nibble RXD2 / I2C:SDA PD18 / FCC1:UTOPIA8:RXADDR4 / FCC1:UTOPIA8:RXCLAV3 / SPI:SPICLK PD16 / FCC1:UTOPIA8:TXPRTY / SPI:SPIMISO NMI RSTCONF GNDSYN1 PA13 / FCC1:UTOPIA8:RXD3 / SDMA:MSNUM2 PA10 / FCC1:UTOPIA8:RXD0 / SDMA:MSNUM5 PA8 / SMC2:SMRXD / TDMA1:serial L1RXD / TDMA1:nibble L1RXD0 SPARE5 ARTRY TBST TT2 A4 A8 A11 A17 A18 PB23 / FCC2:MII and HDLC nibble:TXD1 / TDMA1:nibble:L1RXD2 / TDMD2:L1TXD PD19 / FCC1:UTOPIA8:TXADDR4 / FCC1:UTOPIA:TXCLAV3 / SPI:SPISEL / BRG1O PC15 / FCC1:UTOPIA8:TXADDR0 / SCC1:CTS/CLSN / SMC2:SMTXD PC12 / FCC1:UTOPIA8:RXADDR1 / SCC2:CD/RENA / SI1:LIST3 NMI_OUT HRESET GNDSYN PA11 / FCC1:UTOPIA8:RXD1 / SDMA:MSNUM4 PD7 / FCC1:UTOPIA8:TXADDR3 / FCC1:UTOPIA8:TXCLAV2 / SMC1:SMSYN
3-30
Lidded FC-PBGA Package Description
Table 3-2. MSC8103 Signal Listing by Pin Designator (Continued)
Number
V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18
Signal Name
PA7 / SMC2:SMSYN / TDMA1:L1TSYNC ABB / IRQ2 BG TSIZ0 TT3 A2 A6 A9 A13 A14 PA18 / FCC1:UTOPIA8:TXD7 / FCC1:MII and HDLC nibble:TXD0 / FCC1:transparent and HDLC serial:TXD PA15 / FCC1:UTOPIA8:RXD5 / FCC1:MII and HDLC nibble:RXD2 SRESET PORESET TEST VCCSYN PA14 / FCC1:UTOPIA8 RXD4 / FCC1:MII and HDLC nibble:RXD3 PA9 / SMC2:SMTXD / TDMA1:serial:L1TXD /TDMA1:nibble:L1TXD0 PC5 / FCC2:CTS / SMC1:SMTXD / SI2:LIST3 IRQ7 / INT_OUT TSIZ2 TSIZ1 TT4 A0 A5 A7 A10
3-31
Lidded FC-PBGA Package Mechanical Drawing
3.3 Lidded FC-PBGA Package Mechanical Drawing
Notes: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions in millimeters. 3. Maximum solder ball diameter measured parallel to Datum A. 4. Primary Datum A and the seating plane are defined by the spherical crowns of the solder balls.
CASE 1473-01 Figure 3-3. MSC8103 Mechanical Information, 332-pin Lidded FC-PBGA Package
3-32
Chapter 4
Design Considerations
4.1 Thermal Design Considerations
An estimation of the chip-junction temperature, TJ, in C can be obtained from the following:
Equation 1: TJ = TA + (PD *
where
JA)
TA = ambient temperature C PD = PINT + PI/O in W
JA = package thermal resistance, junction to ambient, C/W
PINT = IDD x V DD in W--chip internal power PI/O = power dissipation on output pins in W--user determined The user should set TA and PD such that TJ does not exceed the maximum operating conditions. In case TJ is too high, the user should either lower the ambient temperature or the power dissipation of the chip.
4-1
Electrical Design Considerations
4.2 Electrical Design Considerations
The input voltage must not exceed the I/O supply VDDH by more than 2.5 V at any time, including during power-on reset. In turn, VDDH can exceed VDD/VCCSYN by more than 3.3 V during power-on reset, but for no more than 100 ms. VDDH should not exceed VDD/VCCSYN by more than 2.1 V during normal operation. VDD/VCCSYN must not exceed VDDH by more than 0.4 V at any time, including during power-on reset. Therefore the recommendation is to use "bootstrap" diodes between the power rails, as shown in Figure 4-1.
I/O Power
MUR420 MUR420 MUR420
3.3 V (VDDH)
Core/PLL Supply
MUR420
1.6 V (VDD/VCCSYN)
Figure 4-1. Bootstrap Diodes for Power-Up Sequencing Select the bootstrap diodes such that a nominal V DD/VCCSYN is sourced from the VDDH power supply until the VDD/VCCSYN power supply becomes active. In Figure 4-1, four MUR420 Schottky barrier diodes are connected in series; each has a forward voltage (VF) of 0.6 V at high currents, so these diodes provide a 2.4 V drop, maintaining 0.9 V on the 1.6 V power line. Once the core/PLL power supply stabilizes at 1.6 V, the bootstrap diodes will be reverse biased with negligible leakage current. The VF should be effective at the current levels required by the processor. Do not use diodes with a nominal VF that drops too low at high current.
4.3 Power Considerations
The internal power dissipation consists of three components: PINT = PCORE + PSIU + PCPM Power dissipation depends on the operating frequency of the different portions of the chip. Table 2-5 provides typical power values at the specified operating frequencies. To determine the typical power dissipation for a given set of frequencies, use the following equations: PCORE (f) = ((PCORE - PLCO)/fCORE) x fCOREA + PLCO PCPM (f) = ((PCPM - PLCP)/fCPM) x fCPMA + PLCP PSIU (f) = ((PSIU - PLSI)/fSIU) x fSIUA + PLSI Where: -- fCORE is the core frequency, fSIU is the SIU frequency, and fCPM is the CPM frequency specified in Table 2-5 in MHz -- fCOREA is the actual core frequency, FSIUA is the actual SIU frequency, and FCPMA is the actual CPM frequency in MHz -- PLCO, PLSI, and PLCP are the leakage power values specified in Table 2-5 -- All power numbers are in mW -- Power consumption is assumed to be linear with frequency. The first part of each equation computes a mw/MHz value that is then scaled based on the actual frequency used.
4-2
Power Considerations
To determine a total power dissipation in a specific application, you must add the power values derived from the above set of equations to the value derived for I/O power consumption using the following equation for each output pin:
Equation 2: P = C x VDDH2 x f x 10-3
Where: P = power in mW, C = load capacitance in pF, f = output switching frequency in MHz. For an application in which external data memory is used in a 32-bit single bus mode and no other outputs are active, the core runs at 200 MHz, the CPM runs at 100 MHz and the SIU runs at 50 MHz, power dissipation is calculated as follows: Assumptions: * * * * External data memory is accessed every second cycle with 10% of address pins switching. External data memory writes occurs once every eight cycles with 50% of data pins switching. Each address and data pin has a 30 pF total load at the pin. The application operates at VDDH = 3.3 V.
Since the address pins switch once at every second cycle, the address pins frequency is a quarter of the bus frequency (that is, 25 MHz). For the same reason the data pins frequency is 3.125 MHz. Table 4-1. Power Dissipation
Pins
Address Data, HRD, HRW CLKOUT Total PI/O
# of pins switching
4 34 1
xC
x 30 x 30 x 30
x VDDH2
x 3.32 x 3.32 x 3.32
x f x 10-3
x 12.5 x 10-3 x 3. 125 x 10-3 x 50 x 10-3
Power in mW
16.25 34.75 16 67
Calculating internal power (from Table 2-5 values): PCORE (200) = ((PCORE - PLCO)/300) x 200 + PLCO =((450 - 3) / 300 x 200 + 3 = 301 PCPM (100) = ((PCPM - PLCP) / 200) x 100 + PLCP = ((320 - 6) / 200) x 100 + 6 = 163 PSIU (50) = ((PSIU - PLSI) / 100) x 50 + PLSI = ((80 - 2) / 100) x 50 + 2 = 41 PINT = PCORE(200) + P CPM(100) + P SIU(50) = 301 + 163 + 41 = 505 PD = PINT + PI/O = 505 + 67 = 572 Maximum allowed ambient temperature is: TA = TJ - (PD x JA)
4-3
Layout Practices
4.4 Layout Practices
Each VCC and VDD pin on the MSC8103 should be provided with a low-impedance path to the board's power supply. Similarly, each GND pin should be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on the chip. The VCC power supply should be bypassed to ground using at least four 0.1 F by-pass capacitors located as closely as possible to the four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip VCC, VDD, and GND should be kept to less than half an inch per capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and GND planes. All output pins on the MSC8103 have fast rise and fall times. Printed circuit board (PCB) trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times. This recommendation particularly applies to the address and data busses. Maximum PCB trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PCB traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the VCC, VDD, and GND circuits. Pull up all unused inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins. There are 2 pairs of PLL supply pins: VCCSYN-GND SYN and VCCSYN1-GNDSYN1. Each pair supplies one PLL. To ensure internal clock stability, filter the power to the VCCSYN and VCCSYN1 inputs with a circuit similar to the one in Figure 4-2. To filter as much noise as possible, place the circuit as close as possible to VCCSYN and VCCSYN1. The 0.01-F capacitor should be closest to VCCSYN and VCCSYN1, followed by the 10-F capacitor, the 10-nH inductor, and finally the 10- resistor to VDD. These traces should be kept short and direct.
GNDSYN and GNDSYN1 should be provided with an extremely low impedance path to ground and should be bypassed to VCCSYN and VCCSYN1, respectively, by a 0.01-F capacitor located as close as possible to the chip package. The user should also bypass GND SYN and GNDSYN1 to VCCSYN and VCCSYN1 with a
0.01-F capacitor as closely as possible to the chip package
VDD 10 10nH 10 F
VCCSYN
0.01 F
Figure 4-2. VCCSYN and VCCSYN1 Bypass
4-4
Index
A
AC timings 2-8 Address Acknowledge signal 1-10 Address Bus Busy signal 1-9 Address Bus signal 1-8 Address Latch Enable (ALE) 1-16 Address Retry signal 1-10 applications iv
D
Data Bus 1-11 Data Bus Bit 32-47 signals 1-10 Data Bus Bit 48-51 signals 1-10 Data Bus Bit 52 signal 1-11 Data Bus Bit 53 signal 1-11 Data Bus Bit 54 signal 1-11 Data Bus Bit 55 signal 1-11 Data Bus Bit 56 signal 1-12 Data Bus Bit 57 signal 1-12 Data Bus Bit 58 signal 1-12 Data Bus Bit 59 signal 1-12 Data Bus Bit 60 signal 1-12 Data Bus Bit 61-63 signals 1-12 Data Bus Busy signal 1-10 Data Bus Grant signal 1-10 Data Bus Most Significant Word (D[0-31]) 1-10 Data Parity 0 (DP0) 1-13 Data Parity 1 (DP1) 1-13 Data Parity 2 (DP2) 1-13 Data Parity 3 (DP3) 1-13 Data Parity 4 (DP4) 1-14 Data Parity 5 (DP5) 1-14 Data Parity 6 (DP6) 1-14 Data Parity 7 (DP7) 1-14 Data Valid (PSDVAL) 1-15 DC electrical characteristics 2-3 Debug Request (DBREQ) signal 1-6 design considerations electrical 4-2 layout practices 4-4 power 4-2 power dissipation 4-3 thermal 4-1 DMA Acknowledge 3 (DACK3) 1-14 DMA Acknowledge 4(DACK4) 1-14 DMA controller iii DMA Request 3 (DREQ3) 1-14 DMA Request 4 (DREQ4) 1-14 documentation iv
B
block diagram i Boot Mode 0-1 (BTM[0-1]) signals 1-7 Buffer Control 0 (BCTL0) 1-16 Buffer Control 1 (BCTL1) 1-16 Burst Address 27-28 (BADDR[27-28]) 1-16 Burst Address 29 signal 1-9 Burst Address 30 signal 1-9 BUS DF 2-4 Bus Grant signal 1-9 Bus Output Enable signal 1-17 Bus Parity Byte Select signal 1-17 Bus Request signal 1-9 Bus SDRAM A10 signal 1-16 Bus SDRAM Address Multiplexer signal 1-17 Bus SDRAM CAS signal 1-17 Bus SDRAM RAS signal 1-17 Bus SDRAM Write Enable signal 1-16 Bus Transfer Start signal 1-10 Bus UPM General-Purpose Line 0 signal 1-16 Bus UPM General-Purpose Line 1 signal 1-16 Bus UPM General-Purpose Line 2 signal 1-17 Bus UPM General-Purpose Line 3 signal 1-17 Bus UPM General-Purpose Line 4 signal 1-17 Bus UPM General-Purpose Line 5 signal 1-17 Bus UPM Wait signal 1-17 Bus Write Enable (PWE[0-7]) 1-16
C
capabilities iv Chip Select (CS0-7) 1-16 clock 1-5 JTAG 2-25 operation 2-8 clocks System Clock Control Register (SCCR) 2-5 System Clock Mode Register (SCMR) 2-5 CPM inputs 2-22, 2-23
E
electrical characteristics DC 2-3 EOnCE Event 0(EE0) signal 1-6 EOnCE Event 1(EE1) signal 1-6 EOnCE Event 2EE2) signal 1-6 EOnCE Event 3 (EE3) signal 1-6 Index-1
Index
EOnCE Event 4 (EE4) signal 1-7 EONCE Event 5 (EE5) signal 1-7 EOnCE Event Detection (EED) signal 1-7 External Bus Grant 2 (EXT_BG2) 1-13 External Bus Grant 3 (EXT_BG3) 1-14 External Bus Request 3 (EXT_BR3) 1-13 External Data Bus Grant 2 (EXT_DBG2) 1-13 External Data Bus Grant 3 (EXT_DBG3) 1-14 External PPC Bus Request 2 (EXT_BR2) 1-13
Host Read Write Select signal 1-11 Host Request (HREQ) 1-11 Host Write Data Strobe (HWR) 1-11 HRESET 1-7
I
input voltage 2-2 inputs CPM 2-22, 2-23 Interrupt Output (INT_OUT) 1-15 Interrupt Request 1 (IRQ1) 1-13 Interrupt Request 2 (IRQ2) 1-9, 1-13 Interrupt Request 3 (IRQ3) 1-9, 1-10, 1-13 Interrupt Request 4 (IRQ4) 1-14 Interrupt Request 5 (IRQ5) 1-9, 1-14 Interrupt Request 6 (IRQ6) 1-14 Interrupt Request 7 (IRQ7) 1-14, 1-15
F
FCC internal clock diagram 2-23 FC-PBGA mechanical drawing 3-32 features DMA controller iii enhanced 16-bit parallel Host Interface (HID16) iii on-chip SRAM iii PLLs iii process technology iii programmable memory controller iii SC140 core iii small foot print package iii very low power consumption iii frequencies maximum 2-4 functional signal groups 1-1
J
JTAG Port reset timing diagram 2-26 timing 2-25 JTAG signals 2-25 junction temperature 2-2
L
layout practices 4-4
G
Global signal 1-8 GPCM TA signal 1-17
M
maximum frequencies 2-4 maximum ratings 2-2 maximum ratings, 2-2 MSC8103 block diagram i description i
H
H8BIT (H8BIT) 1-12 HDI08 timing 2-17 HID16 iii Host Acknowledge (HACK) 1-12 Host Address Line 0 signal 1-10 Host Chip Select signal 1-11 Host Data signal 1-10 Host Data Strobe (HDS) 1-11 Host Data Strobe Polarity (HDSP) 1-12 Host Dual Data Strobe (HDDS) 1-12 host interface iii Host Interface timing 2-17 Host Port Enable(HPE) signal 1-6 Host Read Strobe signal 1-11 Index-2
N
networking capabilities iv Non-Maskable Interrupt (NMI) 1-15 Non-Maskable Interrupt Output(NMI_OUT) 1-15 non-multiplexed bus timings read 2-19, 2-20 write 2-20, 2-21
P
package iii
Index
FC-PBGA description 3-32 pinout bottom view 3-3 top view 3-2 PIO, timer, and DMA signal diagram 2-24 PLLs iii PORESET 1-7 power 1-4 power considerations 4-2 power consumption iii power dissipation 4-3 power-on reset flow 2-9 process technology iii product documentation iv programmable memory controller iii
R
Receive Host Request (HRRQ) 1-12 reset actions 2-9 determine the PLL locking mode 2-9 external configuration signals Boot Mode 2-10 EONCE Event Bit 0 2-10 Host Port Enable 2-10 Reset Configuration 2-10 hard reset 2-9 hardware reset configuration 2-9 host reset configuration 2-9 PORESET 2-11 power-on reset flow 2-9 program reset configuration word via the Host port 2-11 reset causes 2-9 reset sources 2-9 RSTCONF 2-11 soft reset 2-9 RSTCONF 1-7
S
SC140 core iii SCC/SMC/SPI/I2C external clock diagram 2-24 SCC/SMC/SPI/I2C internal clock diagram 2-23 SDRAM DQM (PSDDQM[0-7]) 1-16 signal groupings 1-1 signals 1-1 external 1-2 JTAG 2-25 memory controller
tick spacing 2-13 multiplexed 1-1 signals, external Address Acknowledge (AACK) 1-10 Address Bus (A[0-31]) 1-8 Address Bus Busy (ABB) 1-9 Address Retry (ARTRY) 1-10 Burst Address 29 (BADDR29) 1-9 Burst Address 30 (BADDR30) 1-9 Bus Grant 1-9 Bus Grant (BG) 1-9 Bus Output Enable (POE) 1-17 Bus Parity Byte Select (PPBS) 1-17 Bus request signal (BR) 1-9 Bus SDRAM A10 (PSDA10) 1-16 Bus SDRAM Address Multiplexer (PSDAMUX) 1-17 Bus SDRAM CAS (PSDCAS) 1-17 Bus SDRAM RAS (PSDRAS) 1-17 Bus SDRAM Write Enable (PSDWE) 1-16 Bus Transfer Start (TS) 1-10 Bus UPM General Purpose Line 1 (PGPL1) 1-16 Bus UPM General-Purpose Line 0 (PGPL0) 1-16 Bus UPM General-Purpose Line 2 (PGPL2) 1-17 Bus UPM General-Purpose Line 3 (PGPL3) 1-17 Bus UPM General-Purpose Line 4 1-17 Bus UPM General-Purpose Line 4 (PGPL4) 1-17 Bus UPM General-Purpose Line 5 (PGPL5) 1-17 Data Bus Bit 48-51 (D[48-51]) 1-10 Data Bus Bit 52 (D52) 1-11 Data Bus Bit 53 (D53) 1-11 Data Bus Bit 54 (D54) 1-11 Data Bus Bit 55 (D55) 1-11 Data Bus Bit 56 (D56) 1-12 Data Bus Bit 57 (D57) 1-12 Data Bus Bit 58 (D58) 1-12 Data Bus Bit 59 (D59) 1-12 Data Bus Bit 60 (D60) 1-12 Data Bus Bit 61-63 (D[61-63]) 1-12 Data Bus Bits 32-47 (D[32-47] ) 1-10 Data Bus Busy (DBB) 1-10 Data Bus Grant (DBG) 1-10 Global (GBL) 1-8 GPCM TA (PGTA) 1-17 Index-3
Index
Host Address Line 0 (HA0) 1-10 Host Chip Select (HCS) 1-11 Host Data (H[0-15]) 1-10 Host Read Strobe (HRD) 1-11 Host Read Write Select 1-11 Interrupt Request 1 (IRQ1) 1-13 Interrupt Request 2 (IRQ2) 1-9, 1-13 Interrupt Request 3 (IRQ3) 1-9, 1-10, 1-13 Interrupt Request 4 (IRQ4) 1-14 Interrupt Request 5 (IRQ5) 1-9, 1-14 Interrupt Request 6 (IRQ6) 1-14 Interrupt Request 7 (IRQ7) 1-14, 1-15 Spare Pins (SPARE1, 5) 1-45 signals, external Bus UPM Wait (PUPMWAIT) 1-17 Spare Pins signal 1-45 SPLL MF 2-4 SPLL multiplication factor 2-4 SPLL PDF 2-4 SRAM iii SRESET 1-7 storage temperature 2-2 supply voltage 2-2 System Clock Control Register (SCCR) 2-5 System Clock Mode Register (SCMR) 2-6
T
TAP timing diagram 2-25 target applications iv TDM signal diagram 2-24 Test Clock (TCK) input timing diagram 2-25 thermal design considerations 4-1 thermal characteristics 2-3 timing interrupt 2-10 mode select 2-10 Reset 2-10 Stop 2-10 timings AC 2-8 Transfer Acknowledge (TA) 1-14 Transfer Error Acknowledge (TEA) 1-15 Transmit Host Request (HTRQ) 1-11
U
UPM Byte Select (PBS) 1-16
Index-4
Ordering Information
Consult a Motorola Semiconductor sales office or authorized distributor to determine product availability and place an order.
Core Frequency (MHz) 275 300
Part
Supply Voltage 1.6 V core 3.3 V I/O
Package Type
Pin Count 332
Order Number
MSC8103
Lidded Flip Chip Plastic Ball Grid Array (FC-PBGA)
MSC8103M1100F MSC8103M1200F
HOW TO REACH US:
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MSC8103/D, REV. 7

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